Solid state imaging device having a constant pixel integrating period and blooming resistance

A solid state imaging device comprising:

• a pixel group containing Charge Modulation Devices as pixels and prepared by arraying said pixels in the form of a matrix, wherein each said Charge Modulation Device includes gate, source, and drain terminals,
• a plurality of row lines each commonly connected to respective gate terminals of those pixels in said pixel group which are arrayed in the X-direction for each row,
• a plurality of column lines each commonly connected to respective source terminals of those pixels in said pixel group which are arrayed in the Y-direction for each column,
• a vertical scanning circuit for sequentially selecting successive rows of said row lines by applying a pixel readout driving signal to said row lines from line-to-line, wherein a signal is applied to non-selected rows of said row lines which forms an integrating voltage during a horizontal blanking period and which forms an overflow voltage during a horizontal video effective period, said vertical scanning circuit also applying to each selected row said pixel readout driving signal consisting of a first readout voltage, a reset voltage and a second readout voltage during the horizontal blanking period and also a signal forming an overflow voltage during the horizontal video effective period,
• first storage means provided for each of said column lines to simultaneously store video signal currents of all pixels in that row line which is applied with said pixel readout driving signal from said vertical scanning circuit to provide a constant pixel integrating period and a constant blooming resistance, the video signal currents being obtained in response to said first readout voltage before resetting,
• second storage means provided for each of said column lines to simultaneously store dark-site offset currents of all pixels in that row line which is applied with said pixel readout driving signal from said vertical scanning circuit, the dark-state offset currents being obtained in response to said second readout voltage just after resetting,
• a horizontal scanning circuit for delivering drive signals to sequentially output the video signal currents stored in said first storage means and the dark-state offset currents stored in said second storage means separately from each other, and
• means for outputting differences between the video signal currents and the dark-state offset currents both being sequentially outputted.

A solid state imaging device comprising:

• a pixel group containing Charge Modulation Devices as pixels and prepared by arraying said pixels in the form of a matrix, wherein each said Charge Modulation Device includes gate, source and drain terminals,
• a plurality of row lines each commonly connected to respective gate terminals of those pixels in said pixel group which are arrayed in the X-direction for each row,
• a plurality of column lines each commonly connected to respective source terminals of those pixels in said pixel group which are arrayed in the Y-direction for each column,
• a vertical scanning circuit for sequentially selecting successive rows of said row lines by applying a pixel readout driving signal to said row lines from line-to-line, wherein a signal is applied to non-selected rows of said row lines which forms an integrating voltage during a horizontal blanking period and which forms an overflow voltage during a horizontal video effective period, said vertical scanning circuit also applying to each selected row said pixel readout driving signal consisting of a first readout voltage, a reset voltage and a second readout voltage during the horizontal blanking period and also a signal forming an overflow voltage during the horizontal video effective period,
• first storage means provided for each of said column lines to simultaneously store video signal currents of all pixels in that row line which is applied with said pixel readout driving signal from said vertical scanning circuit to provide a constant pixel integrating period and a constant blooming resistance, the video signal currents being obtained in response to said first readout voltage before resetting,
• second storage means having a polarity opposite to the polarity of said first storage means and provided for each of said column lines to simultaneously store dark-state offset currents of all pixels in that row line which is applied with said pixel readout driving signal from said vertical scanning circuit, the dark-state offset currents being obtained in response to said second readout voltage just after resetting, and
• a horizontal scanning circuit for delivering drive signals to sequentially output differential currents between the video signal currents stored in said first storage means and the dark-state offset currents stored in said second storage means.