US 5,276,513 AGranted

Implementation architecture for performing hierarchical motion analysis of video images in real time

AssigneeRCA Thomson Licensing Corporation

InventorsGooitzen S. van der Wal, Joseph O. Sinniger, Charles H. Anderson

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Abstract

First circuit apparatus, comprising a given number of prior-art image-pyramid stages, together with second circuit apparatus, comprising the same given number of novel motion-vector stages, perform cost-effective hierarchical motion analysis (HMA) in real time, with minimum system processing delay and/or employing minimum hardware structure. Specifically, the first and second circuit apparatus, in response to relatively high-resolution image data from an ongoing input series of successive given pixel-density image-data frames that occur at a relatively high frame rate (e.g., 30 frames per second), derives, after a certain processing-system delay, an ongoing output series of successive given pixel-density vector-data frames that occur at the same given frame rate. Each vector-data frame is indicative of image motion occurring between each pair of successive image frames.

In an image-processing system, responsive to relatively high-resolution image data from an ongoing input series of successive given pixel-density image-frames that occur at a given frame rate, for deriving, after a certain processing-system delay, an ongoing output series of successive given pixel-density vector-data frames that occur at the same given frame rate, in which each vector-data frame is indicative of image motion occurring between each pair of successive image frames;

wherein said system comprises first hardware means for representing the image data of each single one of said image-frames at n+1 ordinally-arranged successively lower pixel-density levels 0 . . . n within a first time interval equal in length to a given fraction of the certain processing-system delay, where n is a given integer having a value of at least 1, with pixel-density level 0 corresponding to said given pixel density and pixel-density level n corresponding to a lowest pixel density, and wherein said system further comprises:
second hardware means, incorporating at least one image buffer means, at least one image warp means, at least one motion-analysis means, at least one pixel-density expand means, and at least one adder means, for sequentially employing said image data of each pair of successive image-frames at each of said pixel-density levels n . . . n-k (k an integer less than or equal to n) to derive, within a second time interval equal in length to a remaining fraction of the certain processing-system delay, a separate motion vector for each pixel at each of said pixel-density levels n . . . n-k, starting with said lowest pixel-density n, for that pair of successive image-frames, by adding a residual motion vector for that pixel derived at each of said pixel-density levels above said lowest pixel-density n to the corresponding separate motion vector already derived at its immediately lower pixel-density level;
whereby a motion-vector map at n-k pixel-density may be derived in real time in response to each pair of successive given pixel-density image-frames of the ongoing input series.

Abstract

Claims19