Method of forming insulated gate field-effect transistors

A process for fabricating an insulated-gate field-effect transistor having reduced gate insulator stress, comprising the steps of:

• forming a first tank region in which the semiconductor portions of the insulated-gate field-effect transistor are to be contained;
• forming a second tank region of a second conductivity type opposite the conductivity type of the first tank region, and to be contained within the first tank region;
• and
• forming a control gate to be insulatively adjacent a semiconductor channel region of the transistor so as to control the conductance thereof after the process is completed, said control gate formed such that a lateral margin of the second tank region is beneath the first portion of the control gate;
• selectively modifying a first portion of the control gate to be substantially conductive;
• during said step of selectively modifying, masking a second portion of the control gate such that it will remain substantially nonconductive;
• forming a semiconductor source region adjacent the first portion of the control gate;
• and
• forming a semiconductor drain region substantially adjacent the second portion of the control gate.