Multi-mode digital to analog converter and method
AssigneeTexas Instruments Incorporated
InventorsSabrina D. Phillips, James R. Hochschild, William A. Severin
Life of this patent
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Abstract
A multi-mode digital to analog converter for converting a digital input into an analog voltage according to a linear or a companding transfer function. The converter comprises a charge redistribution device for creating an analog voltage at a node and switching circuitry for controlling the charge redistribution device. The switching circuitry is operable to effect either transfer function responsive to its inputs.
Claims7
A multi-mode digital to analog convertor, comprising:
- a first capacitor array for generating a first voltage at a first node, each capacitor in the array having a first and second terminal, each of the first terminals coupled to the first node;
- a second capacitor array for generating a second voltage at a second node, each capacitor in the second array having a first and second terminal, each of the first terminals of the second capacitor array coupled to the second node;
- and
- switching circuitry coupled to the first and second array, the circuitry operable to control the first and second arrays for converting a digital input to an analog output according to a linear transfer function upon the switching circuitry receiving a first input control signal, the circuitry operable to control the first and second arrays for converting the digital input to an analog output according to a companding transfer function responsive to receiving a second input control signal.
A multi-mode digital to analog converter comprising:
- a first capacitor array for generating a first voltage at a first node, each capacitor in the array having a first and second terminal, each of its first terminals coupled to the first node;
- a second capacitor array for generating a second voltage at a second node, each capacitor in the array having a first and second terminal, each of its first terminals coupled to the second node;
- a first scaling capacitor having first and second terminals, its terminal coupled to the first node and the s terminal coupled to a third node;
- switching circuitry for accepting a set of inputs, for coupling the second terminal of each of the capacitors of the first array to one of a first set of voltage levels, and for coupling the second terminal of each of the capacitors of the second array to one of a second set of voltage levels including a voltage at the third node, the switching circuitry responsive to the set of digital inputs, one of the set of inputs representative of a selected transfer function, the transfer function selected from the group consisting of linear and companding;
- and
- a buffer for outputting the voltage on the second node.
A method for generating an analog voltage at an output node representative of a digital input and a selected transfer function comprising the steps of:
- generating a first voltage at a first node, the first node coupled to each of a first terminal of a first array of capacitors, each of a second terminal of the first array of capacitors selectively coupled to one of a first set of voltage levels the selected one of the first set of voltage levels responsive to the digital input;
- and
- generating a second voltage at the output node, the output node coupled to each of a first terminal of a second array of capacitors, each of a second terminal of the second array of capacitors selectively coupled to one of a second set of voltage levels including a voltage at a third node, the third node coupled to the first node through a scaling capacitor, the selected one of the second set of voltage levels responsive to the digital input and to the transfer function, the transfer function selected from the group consisting of linear and companding.
Dependencies are inferred from the claim text.