Method and structure for programming floating gate memory cells

Abstract

A novel method and structure are taught for narrowing the distribution of charge on the floating gates after electrical erasure of a population of cells. This allows faster programming following erasure. An additional recovery step is performed after erasure and prior to programming. The recovery step serves to adjust the state of erasure of the cells such that the distribution of the amount of erasure of each cell in the population of cells is reduced. This is accomplished in order to cause those cells which would have a relatively high floating gate voltage V.sub.FG after erasure to be recovered such that their floating gate voltage is made less positive, while having little or no effect on the floating gate voltage of cells which are not overerased. The recovery is performed either as a final step in the erase operation, a separate recovery step independent of the erase or program operations, or as a preliminary step during the programming operation. Recovery can be performed on all memory cells simultaneously, blocks or groups of memory cells in sequence, or individual memory cells in sequence. The recovery step is performed utilizing a low control gate voltage, which voltage is approximately equal to or slightly greater than the threshold voltage of the select transistor, which generates a relatively high floating gate current for over-erased cells, causing them to be significantly less over-erased.

Dependencies are inferred from the claim text.