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US 5,272,600 AGranted
Electrical interconnect device with interwoven power and ground lines and capacitive vias
AssigneeMicroelectronics and Computer Technology Corporation
InventorDavid H. Carey
Life of this patent
Estimating the term…
Abstract
The invention relates to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of otherwise undedicated area between signal lines and signal layers and to reduce or eliminate the need for separate power and ground layers while providing decoupling capacitance within the wiring structure.
Claims23
An electrical interconnect device, comprising:
- a plurality of spaced, parallel, conductive upper lines in an upper horizontal plane comprising upper signal lines and upper power distribution lines wherein an upper signal line is between each pair of upper power distribution lines and an upper power distribution line is between each pair of upper signal lines;
- a plurality of spaced, parallel, conductive lower lines in a lower horizontal plane comprising lower signal lines and lower power distribution lines wherein a lower signal line is between each pair of lower power distribution lines and a lower power distribution lines is between each pair of lower signal lines, and the lower lines are positioned beneath, spaced from and orthogonal to the upper lines;
- a plurality of vertical, conductive vias between and connected to the upper and lower lines comprising signal vias located at selected overlapping regions of the upper and lower signal lines and power distribution vias located at selected overlapping regions of the upper and lower power distribution lines;
- and
- a plurality of vertical, capacitive vias between and connected to selected upper and lower power distribution lines.
2 more elements
An electrical interconnect device, comprising:
- a plurality of spaced, parallel, metallic first electrical signal lines in an upper horizontal plane;
- a plurality of spaced, parallel, metallic lower electrical signal lines in a lower horizontal plane with the lower signal lines positioned beneath, spaced from and orthogonal to the upper signal lines;
- a plurality of spaced, parallel, metallic upper power lines in the upper plane arranged parallel to and spaced from the upper signal lines;
- a plurality of spaced, parallel, metallic lower power lines in the lower plane arranged parallel to and spaced from the lower signal lines;
- a plurality of spaced, parallel, metallic upper ground lines in the upper plane arranged parallel to and spaced from the upper signal and upper power lines;
- a plurality of spaced, parallel, metallic lower ground lines in the lower plane arranged parallel to and spaced from the lower signal and lower power lines;
- a plurality of conductive, vertical signal vias located between and connecting selected upper and lower signal lines;
- a plurality of conductive, vertical power vias located between and connecting the upper and lower power lines;
- a plurality of conductive, vertical ground vias located between and connecting the upper and lower ground lines;
- and
- a plurality of vertical capacitive vias, wherein some of the capacitive vias are located between and connecting the upper power lines to the lower ground lines, and other capacitive vias are located between and connecting the upper ground lines to the lower power lines.
8 more elements
An electrical electrical interconnect device having a supportive base, alternating insulating and metallization layers, and semiconductor integrated circuit chips mounted thereon, said device comprising:
- a supportive base;
- a plurality of spaced, elongated, parallel upper electrical signal lines in an upper horizontal plane above the base;
- a plurality of spaced, elongated, parallel lower electrical signal lines in a lower horizontal plane above the base wherein the lower signal lines are positioned beneath, spaced from and orthogonal to the upper signal lines;
- a plurality of spaced, elongated, parallel upper power lines in the upper plane arranged parallel to and spaced from the upper signal lines, wherein each upper power line between at least two other upper power lines is between and adjacent to two upper signal lines;
- a plurality of spaced, elongated, parallel lower power lines in the lower plane arranged parallel to and spaced from the lower signal lines, wherein each lower power line between at least two other lower power lines is between and adjacent to two lower signal lines;
- a plurality of spaced, elongated, parallel upper ground lines in the upper plane arranged parallel to and spaced from the upper signal and upper power lines, wherein each upper ground line between at least two other upper ground lines is between and adjacent to two upper signal lines;
- a plurality of spaced, elongated, parallel lower ground lines in the lower plane arranged parallel to and spaced from the lower signal and lower power lines, wherein each lower ground line between at least two other lower ground lines is between and adjacent to two lower signal lines;
- wherein each upper signal line between at least two other upper signal lines is adjacent to an upper power line and an upper ground line and wherein each lower signal line between at least two other lower signal lines is adjacent to a lower power line and a lower ground line;
- wherein each power line and each ground line is wider than each signal line and wherein each signal line is wider than each spacing between adjacent lines in the same plane;
- a plurality of conductive, vertical signal vias which connect selected upper and lower signal lines wherein the signal vias are located at the overlapping regions of the selected upper and lower signal lines;
- a plurality of conductive, vertical power vias which connect selected upper and lower power lines wherein the power vias are located at the overlapping regions of the selected upper and lower power lines;
- a plurality of conductive, vertical ground vias which connect selected upper and lower ground lines wherein the ground vias are located at the overlapping regions of the selected upper and lower ground lines;
- a first plurality of capacitive vias which connect selected upper power lines to selected lower ground lines wherein the first plurality of capacitive vias are located at the overlapping regions of the selected upper power lines and lower ground lines;
- a second plurality of capacitive vias which connect selected upper ground lines to selected lower power lines wherein the second plurality of capacitive vias are located at the overlapping regions of the selected upper ground lines and lower power lines;
- a dielectric material covering the base, surrounding the lines and vias, and having a top surface above the upper and lower planes;
- a plurality of bonding pads on the top surface of the dielectric material wherein a first bonding pad is connected to a signal line, a second bonding pad is connected to a power line, and a third bonding pad is connected to a ground line;
- and
- a plurality of integrated circuits chips mounted on the top surface of the dielectric and connected to the bonding pads.
15 more elements
Dependencies are inferred from the claim text.