Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams)

An integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:

• a) defining PMOS and NMOS regions, and forming multi-level layers of conductive and non-conductive transistor gate materials extending across a memory array section and an adjacent peripheral array section of a semiconductor substrate being processed to form a semiconductor device;
• b) photo-defining n-channel transistor gates within said memory array section and within NMOS regions in said peripheral array section, while leaving in place said gate electrode layers over future transistor regions within PMOS regions in said peripheral array section;
• c) implanting n-type dopant ions into regions of said memory array section adjacent to said n-channel transistor gates for bit or digit lines for said n-channel transistors and into said NMOS regions in said peripheral array section;
• d) depositing and etching dielectric spacers simultaneously into digit lines of said memory array section into said NMOS regions in said peripheral array section, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section;
• p1 e) implanting source/drain regions into said memory array section into said NMOS regions in said peripheral array section;
• f) depositing a dielectric layer;
• g) etching through the deposited dielectric layer in order to form bit contact openings;
• h) depositing a further conductive layer;
• i) defining p-channel transistors;
• j) simultaneously forming spacers for both digit lines and PMOS transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors, wherein said dielectric spacers for bit lines isolate digit line sidewalls from subsequent storage capacitor plates;
• k) forming a capacitor structures in said memory array, wherein conducting transistor gate material forming the word liens in the array and NMOS and PMOS transistors in the periphery have identical film structures;
• l) photo-defining p-channel transistor gates within said peripheral array section of said semiconductor substrate, while leaving said memory array section thereof masked against ion implantation;
• and
• m) subsequent to the step of forming dielectric spacers simultaneously to digit lines and PMOS transistors, implanting dopant ions into regions of said peripheral array section adjacent to transistor gates therein.

A DRAM integrated circuit having complementary n-channel and p-channel devices therein and fabricated by the process of:

• a) patterning NMOS and word line transistors;
• b) subsequent to patterning said NMOS and word line transistors, forming identical dielectric spacers for bit lines and NMOS transistors source/drain areas, and future isolation of wordlines and bitlines, thereby forming identical spacers on both said memory array section into said NMOS regions in said peripheral array section;
• c) digit line deposition and patterning;
• d) subsequent to said forming of said dielectric spacers and subsequent to said digit line deposition, patterning p channel semiconductor material;
• e) simultaneously forming spacers for both digit lines and p channel transistors, thereby forming identical spacers on both said digit lines and said PMOS transistors, wherein said dielectric spacers for bit lines isolate digit line sidewalls from subsequent storage capacitor plates;
• and
• f) depositing storage capacitor plates, wherein conducting transistor gate material forming the word lines in the array and NMOS and PMOS transistors in the periphery have identical film structures.