Refreshing ferroelectric capacitors

A method of extending the endurance of a memory array having a number of addressable nonvolatile memory cells, each memory cell having a ferroelectric capacitor connectable between a drive line and a bit line, comprising the steps of:

• a) accessing a memory cell of the array to revitalize a ferroelectric capacitor by applying an address to a word line associated with the memory cell to connect the ferroelectric capacitor between the drive line and the bit line;
• b) reading the memory cell by applying a read voltage across the ferroelectric capacitor of the accessed memory cell;
• c) isolating the bit line from a sense amplifier;
• d) when the bit line is isolated from sense amplifier, revitalizing the ferroelectric capacitor of the accessed memory cell by applying a voltage greater than the read voltage across the ferroelectric capacitor via the drive line and the bit line to revitalize the ferroelectric capacitor material;
• and
• e) periodically revitalizing the ferroelectric capacitors of the other memory cells of the array by sequentially repeating steps b) through d).

A ferroelectric memory array powered by a DC supply voltage, comprising:

• an array of memory cells, each cell including a ferroelectric capacitive element;
• circuits for accessing the array to address at least one memory cell;
• a voltage drive circuit for applying a voltage of a first magnitude across the ferroelectric capacitive element of the addressed memory cell during a normal memory read/write operation;
• and
• means for applying a second voltage of a magnitude greater than said first magnitude across the capacitive element of each addressed memory cell during a first refresh operation without increasing said DC supply voltage to revitalize ferroelectric material of the capacitive elements.

A ferroelectric memory array, comprising:

• an array of nonvolatile memory cells, each memory cell including a ferroelectric capacitive element;
• circuits for accessing word lines of the array to address at least one memory cell;
• a bit line common to a number of memory cells for transferring electrical charge thereto from the ferroelectric capacitive elements of the respective addressed memory cells;
• a drive line common to a number of memory cells for applying a drive voltage to ferroelectric capacitive elements;
• and
• a drive circuit comprising a bit line drive circuit and a drive line drive circuit connected respectfully to said bit line and to said drive line for applying a bit line refresh voltage and a drive line refresh voltage directly across the ferroelectric capacitive element of at least one memory cell associated with the drive line and the bit line, said bit line and drive line refresh voltage being greater in amplitude than that applied across the ferroelectric capacitive elements during normal read/write operations.

A ferroelectric memory, comprising:

• a plurality of nonvolatile memory cells, each having a ferroelectric capacitive element;
• at least one bit line and at least one word line connected to at least one said cell;
• at least one drive line connected to said one cell;
• a sense amplifier;
• an isolation transistor for switchably connecting said bit line to said sense amplifier during reading of the cell, and for isolating the bit line from the sense amplifier during revitalization of the ferroelectric capacitive element of the cell;
• and
• a drive circuit operative during refreshing of the cells for applying a voltage between the drive line and the bit line to revitalize the ferroelectric capacitive element of said one cell.

In a memory cell having a ferroelectric capacitor, a switching transistor, a word line, a bit line and a drive line, a method for extending an endurance of the ferroelectric capacitor, comprising the steps of:

• accessing the memory cell by addressing the word line;
• causing a voltage of a first magnitude to be applied across the ferroelectric capacitor to read or write the memory cell with respect to a polarization state;
• counting the number of memory access cycles to which the memory cell has been subjected, and on a predefined count, initiating a refresh operation;
• carrying out the refresh operation by applying a voltage of a second magnitude greater than the first magnitude across the ferroelectric capacitor to refresh the ferroelectric material of said capacitor;
• and
• refreshing the cell with increased magnitudes of refresh voltage at each subsequent refresh operation.