Semiconductor read only memory
AssigneeSharp Kabushiki Kaisha
InventorYasuhiro Hotta
Life of this patent
Estimating the term…
Abstract
A semiconductor read only memory with hierarchical bit lines in which a resistance against a discharge current is constant irrespective of the position of a memory cell from which information is to be read is disclosed. A bank selecting MOSFET is connected to one end portion of a sub-bit line. Another bank selecting MOSFET is connected to the other end portion of the adjacent sub-bit line. Bank selecting MOSFETs are connected in the same alternate manner as described above. Therefore, since the resistance on bit lines against the read-out current is constant, a larger read-out current can be used especially when diffusion bit lines are used, whereby the semiconductor read only memory of the invention can achieve a high-speed read operation.
Claims4
A semiconductor read only memory comprising:
- a plurality of first bit lines;
- a plurality of groups of memory cells, in each group, memory cells being electrically connected in parallel between two adjacent ones of said first bit lines;
- second bit lines, the proportion of said second bit lines to said first bit lines being 1 to 2;
- a group of first bank selecting switches each of which is connected between one end of an odd-numbered one of said first bit lines and one end of an odd-numbered one of said second bit liens;
- and
- a group of second bank selecting switches each of which is connected between one end of an even-numbered one of said first bit lines and one end of an even-numbered one of said second bit lines.
Dependencies are inferred from the claim text.