US 5,268,855 AGranted

Common format for encoding both single and double precision floating point numbers

AssigneeHewlett-Packard Company

InventorsRussell W. Mason, Craig A. Heikes

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Abstract

A technique for encoding multiple floating point formats into a double precision floating point number by padding single word floating point numbers with zeros to form a 64-bit double word in a way that allows a single precision arithmetic logic unit to be built on top of a double precision arithmetic logic unit. The formatting circuitry of the invention requires only small differences in the hardware for single and double precision operations so as to simplify the arithmetic logic unit and the multiplier of the floating point processing units. The encoding technique of the invention includes right justifying the exponent and mantissa of the floating point number in a "common format" such that rounding of the mantissa need only occur in one place, thereby greatly simplifying the rounding procedure. The technique of the invention also removes multiplexers from critical speed paths in the floating point processing units when it is desired to accommodate multiple data formats.

Claims4

Dependent claims

A processor for performing floating point operations on input operands, comprising:

a data register for storing operands of at least one of a first and a second precision, where said second precision has a greater number of mantissa bits than said first precision;
a floating point processor for performing floating point mathematical operations on said operands stored in said data register;
and
an operand alignment circuit for converting said operands from said data register into operands in a common format having the precision of said floating point processor and for providing the operands in said common format to said floating point processor for processing, said operand alignment circuit comprising means for aligning least significant bits of exponents and mantissas of operands of both said first and second precisions, means for inserting a predetermined number of bits of a predetermined logic value into the most significant bits of said exponents and mantissas of said operands when converting an operand of said first precision to said common format, and means for eliminating a predetermined number of most significant bits of said exponents and mantissas of results when converting a result from said common format to a result of said first precision.

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Dependencies are inferred from the claim text.