Programmable clock skew adjustment circuit
AssigneeAT&T Bell Laboratories
InventorRichard Muscavage
Life of this patent
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Abstract
An integrated circuit has an oscillator for generating a plurality of phases of an oscillator clock signal. Each phase of the oscillator clock clocks a respective one of a plurality of ring shift registers. The output of each stage of the ring shift registers is a phase of a desired clock signal and is an input to a multiplexer that can selectively provide one of the desired clock phases as the output of the multiplexer. In another embodiment of the invention the ring shift registers generate half of the phases of a desired clock signal at a multiple of the desired frequency. The multiplexer output clocks a divide by two circuit which is followed by another level of multiplexing to generate the other half of the phases and to divide down to the desired frequency.
Claims23
An integrated circuit, comprising:
- an oscillator for generating a plurality of phases of an oscillator clock signal;
- a plurality of multiple stage ring shift registers, each of said ring shift registers clocked by one of the phases of the oscillator clock signal, each stage of each of said plurality of multiple stage ring shift registers providing an output signal;
- and
- a multiplexer having a plurality of inputs adapted to receive said output signals, said multiplexer being responsive to a plurality of control signals for selectively providing one of said plurality of output signals at an output of said multiplexer.
A method for generating phases of a desired clock signal, comprising the steps of:
- generating a plurality of timing signals that are various phases of an oscillator clock signal;
- clocking each stage of a plurality of multiple stage ring shift registers by respective ones of the timing signals;
- and
- selecting an output from one of the shift register stages as an output signal.
A clock skew adjustment circuit, comprising:
- an oscillator clock phase generating circuit for generating a plurality of timing signals that are various phases of an oscillator clock signal;
- a plurality of multiple stage ring shift registers, each of said ring shift registers clocked by one of said timing signals, each stage of each of said plurality of multiple stage ring shift registers providing an output signal;
- and
- a multiplexer having a plurality of inputs adapted to receive said output signals, said multiplexer being responsive to a plurality of control signals for selectively providing one of said plurality of input signals as the output of said multiplexer.
A clock skew adjustment circuit, comprising:
- an oscillator clock phase generating circuit for generating a plurality of timing signals that are various phases of an oscillator clock signal;
- a plurality of multiple stage ring shift registers, each of said ring shift registers clocked by one of said timing signals, at least one stage of each of said plurality of multiple stage ring shift registers providing an output signal;
- and
- a multiplexer having a plurality of inputs adapted to receive said output signals, said multiplexer being responsive to a control signal for selectively providing one of said input signals as the output of said multiplexer.
Dependencies are inferred from the claim text.