Integrated circuit bus structure

An integrated circuit bus structure comprising:

• a plurality of semiconductor integrated circuit dies each having first and second opposed major surfaces and a peripheral edge formed therebetween, the plurality of integrated circuit dies disposed in a spaced, parallel arrangement;
• each of the integrated circuit dies including a plurality of terminal pads disposed on the peripheral edge thereof and electrically connected to the circuitry on each integrated circuit die;
• the terminal pads on each integrated circuit die being arranged in a predetermined, positional electrical signal bus arrangement identical for all of the integrated circuit dies for electrical signal communication to and from each of the plurality of integrated circuit dies, the terminal pads being exposed to a top and a bottom surface of each integrated circuit die;
• and
• electrical conductor means, disposed in electrical signal communication with at least certain of the terminal pads on certain of the integrated circuit dies, to form a multi-bit, parallel bus interconnecting each of the plurality of integrated circuit dies.

An integrated circuit bus structure comprising:

• a plurality of semiconductor integrated circuit dies each having first and second opposed major surfaces and a peripheral edge formed therebetween, the plurality of integrated circuit dies disposed in a spaced, parallel arrangement;
• each of the integrated circuit dies including a plurality of terminal pads disposed on the peripheral edge thereof and electrically connected to the circuitry on each integrated circuit die;
• the terminal pads including electrically conductive pads mounted on the peripheral edges of each integrated circuit die and extending from a top to a bottom surface of each integrated circuit die and over the peripheral edge of each integrated circuit die;
• the terminal pads on each integrated circuit die being arranged in a predetermined, positional electrical signal bus arrangement identical for all of the integrated circuit dies for electrical signal communication to and from each of the plurality of integrated circuit dies;
• and
• electrical conductor means, disposed in electrical signal communication with at least certain of the terminal pads on certain of the integrated circuit dies, to form a multi-bit, parallel bus interconnecting each of the plurality of integrated circuit dies.