Process for manufacturing three dimensional IC's

A process for manufacturing a three dimensional integrated circuit, comprising the steps of:

• I) preparing a first semiconductor substrate having a main surface in which are formed a first integrated circuit comprising element groups having a corresponding space between adjacent element groups and an alignment mark of a first width and first material, formed in the space between said element groups, forming a first insulating layer of a second material on the main surface of the first semiconductor substrate, the second material being different from the first material and the first insulating layer having a top surface, and planarizing said top surface of the first insulating layer of the first semiconductor substrate;
• II) preparing a second semiconductor substrate having a main surface and a back surface and forming a recess in said main surface at a place thereon corresponding to said space of the first semiconductor substrate, said recess of the second semiconductor substrate having a second width greater than the first width of said alignment mark, forming a second insulating layer on the main surface of the second semiconductor substrate so as to bury the recess, and planarizing the second insulating layer, so that the second semiconductor substrate has a planarized top surface, the back surface being opposite said top surface;
• III) aligning the first and second semiconductor substrates with each other, with the first and second insulating layers in facing and contiguous relationship and with said recess of the second semiconductor substrate aligned with said space of the first semiconductor substrate by a light transmitted through the second semiconductor substrate from the back surface thereof, and bonding the aligned substrates to each other at the contiguous and facing first and second insulating layers;
• IV) removing the material of the second semiconductor substrate from the back surface thereof until said second insulating layer, formed in the groove in the main surface, is exposed, and
• V) determining the location of said alignment mark of the first semiconductor substrate, and forming a second integrated circuit in the second semiconductor substrate at a position aligned with first integrated circuit, using said aligning mark of the first semiconductor substrate to determine said position.