Arbitration control logic for computer system having dual bus architecture

A method of arbitrating between input/output devices residing on an input/output bus for control of said input/output bus in a computer system, said system further comprising system memory and a memory controller connected by a memory bus, and a bus interface unit connected at one end to said input/output bus and at the other end to said memory controller by a system bus, said method of arbitration comprising the steps of:

• performing an arbitration cycle with a central arbitration control point residing on said system bus wherein said central arbitration control point arbitrates between input/output devices requesting access to said input/output bus to determine which of said input/output devices should be granted control of said input/output bus;
• performing a grant cycle wherein said central arbitration control point grants control of said input/output bus and extends control of said system bus to one of said input/output devices;
• initiating a read or write operation with said one of said input/output devices to said system memory over said input/output bus, said bus interface unit, and said memory bus;
• temporarily storing in a buffer circuit in said bus interface unit read or write data transferred between said system bus and said input/output bus over said bus interface unit;
• and
• performing a subsequent arbitration cycle simultaneously with the completion of data transfer between said buffer circuit and said system memory over said system bus to complete said read or write operation, in response to a predetermined set of operating conditions.

A computer system, comprising:

• system memory and a memory controller for controlling access thereto, said system memory and said memory controller connected by a memory bus;
• a system device electrically connected with said memory controller;
• a bus interface unit electrically connected to a plurality of input/output devices by an input/output bus and to said memory controller by a system bus, said system device able to initiate write operations to said input/output devices over said system bus, said bus interface unit and said input/output bus, said bus interface unit including a buffer circuit wherein write data transferred between said system bus and said input/output bus over said bus interface unit during said write operation is temporarily stored during the transfer;
• a central arbitration control point residing on said system bus for serially performing (i) arbitration cycles wherein said central arbitration control point arbitrates between said input/output devices having requests pending for access to said input/output bus to determine which of said input/output devices should be granted control of said input/output bus and (ii) grant cycles wherein said central arbitration control point grants control of said input/output bus and extends control of said system bus to one of said input/output devices;
• and
• bus arbitration control logic included in said bus interface unit which permits simultaneous occurrence of (i) arbitration cycles by said central arbitration control point and (ii) completion of data transfer between said buffer circuit and said input/output device over said input/output bus during completion of said write operation.

A method of arbitrating between input/output devices residing on an input/output bus for control of said input/output bus in a computer system, said system further comprising system memory and a memory controller connected by a memory bus, and a bus interface unit connected at one end to said input/output bus and at the other end to said memory controller by a system bus, said method of arbitration comprising the steps of:

• performing an arbitration cycle with a central arbitration control point residing on said system bus wherein said central arbitration control point arbitrates between input/output devices requesting access to said input/output bus to determine which of said input/output devices should be granted control of said input/output bus;
• performing a grant cycle wherein said central arbitration control point grants control of said input/output bus and extends control of said system bus to an input/output device;
• initiating a write operation with a system device attached to said system bus to one of said input/output devices over said memory bus, said bus interface unit, and said input/output bus;
• temporarily storing in a buffer circuit in said bus interface unit write data transferred between said system bus and said input/output bus over said bus interface unit;
• and
• performing a subsequent arbitration cycle simultaneously with the completion of data transfer between said buffer circuit and said one of said input/output devices over said input/output bus to complete said read or write operation.

An arbitration mechanism for arbitrating between input/output devices residing on an input/output bus for control of said input/output bus in a dual bus computer system, said system further comprising system memory and a memory controller connected by a memory bus, and a bus interface unit connected at one end to said input/output bus and at the other end to said memory controller by a system bus, said arbitration mechanism comprising:

• a central arbitration control point residing on said system bus for serially performing (i) arbitration cycles wherein said central arbitration control point arbitrates between input/output devices having requests pending for access to said input/output bus to determine which of said input/output devices should be granted control of said input/output bus and (ii) grant cycles wherein said central arbitration control point grants control of said input/output bus and extends control of said system bus to one of said input/output devices;
• a bus interface unit electrically connected to said memory controller by said system bus and electrically connected to said input/output devices by said input/output bus, said input/output devices able to initiate read or write operations to and from said system memory over said input/output bus, said bus interface unit and said system bus, said bus interface unit including a buffer circuit wherein read or write data transferred between said system bus and said input/output bus over said bus interface unit during said read or write operations is temporarily stored during the transfer;
• and
• bus arbitration control logic included in said bus interface unit which permits simultaneous occurrence of (i) arbitration cycles by said central arbitration control point and (ii) completion of data transfer between said buffer circuit and said system memory over said system bus during completion of one of said read or write operations.

An arbitration mechanism for arbitrating between input/output devices residing on an input/output bus for control of said input/output bus in a dual bus computer system, said system further comprising system memory and a memory controller connected by a memory bus, a bus interface unit connected at one end to said input/output bus and at the other end to said memory controller by a system bus, and a system device attached to said system bus, said arbitration mechanism comprising:

• a central arbitration control point residing on said system bus for serially performing (i) arbitration cycles wherein said central arbitration control point arbitrates between input/output devices having requests pending for access to said input/output bus to determine which of said input/output devices should be granted control of said input/output bus and (ii) grant cycles wherein said central arbitration control point grants control of said input/output bus and extends control of said system bus to one of said input/output devices;
• a bus interface unit electrically connected to a plurality of input/output devices by an input/output bus and to said memory controller said system bus, said system device able to initiate write operations to said input/output devices over said system bus, said bus interface unit and said input/output bus, said bus interface unit including a buffer circuit wherein write data transferred between said system bus and said input/output bus over said bus interface unit during said write operation is temporarily stored during the transfer;
• and
• bus arbitration control logic included in said bus interface unit which permits simultaneous occurrence of (i) arbitration cycles by said central arbitration control point and (ii) completion of data transfer between said buffer circuit and said input/output device over said input/output bus during completion of said write operation.