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US 5,265,047 AGranted
High density SRAM circuit with single-ended memory cells
AssigneeMonolithic System Technology, Inc.
InventorsWingyu Leung, Fu-Chieh Hsu
Life of this patent
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Abstract
A high density, static random access memory (SRAM) circuit with single-ended memory cells employs a plurality of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells employs a single bit-line (BL) and two word lines.
Claims13
A static, random access memory cell comprising:
- a bit line;
- a first word line;
- a second word line;
- a first resistor;
- a second resistor;
- a first transistor having a gate connected to said first word line and a channel having a first end connected to said bit line and a second end coupled by said first resistor to a power supply potential;
- a second transistor having a gate connected to said second word line and a channel having a first end connected to the power supply potential and a second end coupled by said second resistor to the power supply potential;
- a third transistor having a gate connected to said second transistor channel second end and a channel connected between the said first transistor channel second end and a circuit ground potential;
- a fourth transistor having a gate connected to said first transistor channel second end and a channel connected between said second transistor channel second end and the circuit ground potential.
6 more elements
A static, random access memory cell comprising:
- a bit line;
- a first word line;
- a second word line;
- a first transistor having a gate connected to said first word line and a channel having a first end connected to said bit line and a second end;
- a second transistor having a gate connected to said second word line and a channel having a first end connected to the power supply potential and a second end;
- a third transistor having a gate connected to said second transistor channel second end and a channel connected between the said first transistor channel second end and a circuit ground potential;
- and
- a fourth transistor having a gate connected to said first transistor channel second end and a channel connected between said second transistor channel second end and the circuit ground potential;
- a fifth transistor having a gate connected to said second transistor channel second end and a channel connected from said first transistor channel second end to a power supply potential;
- and
- a sixth transistor having a gate connected to said first transistor channel second end and a channel connected from said second transistor channel second end to the power supply potential.
8 more elements
A static random access memory cell comprising:
- a bit line;
- a first source of control signals;
- a second source of control signals;
- a first load having a first end connected to a reference potential;
- a second load having a first end connected to the reference potential;
- a first transistor connecting the second end of the first load to ground;
- a second transistor connecting the second end of the second load to ground;
- a first transfer switch connected between the bit line and a gate of the second transistor and controlled by the control signals from the first source;
- and
- a second transfer switch connected between the reference potential and a gate of the first transistor and controlled by the control signals from the second source;
- wherein a second end of the first load is connected to the gate of the second transistor, and a second end of the second load is connected to the gate of the first transistor.
8 more elements
Dependencies are inferred from the claim text.