High speed arithmetic and logic generator with reduced complexity using negative resistance
OwnerTejinder Singhinventor
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OwnerTejinder Singhinventor
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A technique for generating a carry, AND, OR, NAND, NOR, INVERTING logic and sum and carry: operation in a one or at most two device delay by employing negative differential resistance devices. Circuits implemented with this technique are not only extremely fast, but use a small number of active devices as well. This technique could be implemented in building circuits using any transistor Bipolar Transistors, Field Effect Transistors (FETs), High Electron Mobility Transistors (HEMTs), Hetero-junction Bipolar Transistors (HBTs), etc. The negative differential resistance characteristics of the resonant tunneling transistor can be exploited to increase the noise margin. Resonant tunneling devices have the added advantage of working at very high speeds, and could yield propagation delays less than 5ps.
A carry signal generating device for generating a carry signal, said carry signal generating device has three inputs, said carry signal generating device further comprising:
A device for inverting an input having a first logical state and a second logical state, comprising:
A device for generating a logical output in response to at least two inputs, comprising:
A sum signal generating device for generating a sum signal, said sum signal generating device has five inputs, said sum signal generating device further comprising:
A device for generating a carry signal, said carry signal generating device has three inputs, said carry signal generating device further comprising:
A device for inverting an input having a first logical state and a second logical state, comprising:
A device for generating a logical output in response to at least two inputs, comprising:
A device for generating a logical output in response to at least two inputs, comprising:
Dependencies are inferred from the claim text.