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US 5,262,974 AGranted
Programmable canonic signed digit filter chip
AssigneeTRW Inc.
InventorsJohn C. Hausman, Robert R. Harnden, Etan G. Cohen, Harold G. Mills
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Abstract
A programmable canonic signed digit (CSD) filter is provided which employs programmable CSD multipliers. The filter receives a digital input signal and includes a tapped delay line for providing a delay between the input samples. The filter advantageously employs a plurality of programmable CSD multipliers which receive programmable input filter coefficients and perform multiplication of the coefficient with the delayed input signal. Summation hardware is further included for summing the outputs of the plurality of multipliers to provide the filter output therefrom.
Claims18
A Finite Impulse Response (FIR) digital filter comprising:
- input means for receiving a digital input signal having a plurality of digitized samples;
- delay means having a plurality of delay taps and being connected to said input means for providing a delay between each of said samples;
- first adder means including a plurality of full adders for summing selected pairs of said delayed samples;
- multiplication means including a plurality of programmable canonic signed digit (CSD) multipliers, each of said CSD multipliers receiving a summed sample output from said first adder means and having a plurality of programmable shift paths for multiplying said received output from said first adder means by a programmable filter coefficient so as to generate partial product outputs, wherein said filter coefficient is represented by a variable number of ternary canonic signed digits and wherein each of said programmable shift paths multiplies one of said ternary digits by said summed sample and includes a first logic means for providing a ones complement of the summed sample in each multiplier shift path if said one ternary digit has a negative sign and second logic means for setting the summed sample in an associated shift path to zero so as to disable said associated shift path when not needed;
- and
- second adder means for summing the partial product outputs of said plurality of programmable CSD multipliers to thereby provide a filter output response.
3 more elements
A finite impulse response (FIR) digital filter comprising:
- input means for receiving a digital input signal having a plurality of binary samples;
- a tapped delay line having a plurality of taps connected to said input means for providing a delay between said samples and further including a plurality of adders for summing selected pairs of delayed samples;
- multiplication means including a plurality of programmable canonic signed digit (CSD) multipliers connected to said tapped delay line, each of said programmable CSD multipliers receiving a programmable filter coefficient and multiplying said filter coefficient with one of said summed pair of samples from said tapped delay line via separate programmable shift paths so as to generate partial product outputs, each of said programmable shift paths having logic means including an XOR gate operating on each data bit of said binary samples for inverting each data bit so as to form a ones complement of the input to the associated programmable shift path when desired, said logic means further including an AND gate operating on the output of each of said XOR gates to set to zero the output of the programmable shift path associated therewith when desired, and programmable multiplexers for forming a shifted version of the AND gate outputs;
- compensation means including a register for storing a sum of necessary carry-in bits for providing twos complement inversion of all programmable shift path outputs which were inverted via said XOR gates;
- and
- adder means including a carry save adder tree for summing the partial product outputs of said plurality of programmable CSD multipliers and said programmed summations of carry-in bits from said compensation means to thereby provide a filter output response.
3 more elements
A programmable canonic signed digit (CSD) multiplier comprising:
- first input means for receiving a multiplicand input in twos complement binary form;
- second input means for receiving a canonic signed digit (CSD) multiplier input having a plurality of ternary digits;
- a plurality of programmable shift paths, each shift path receiving said multiplicand input and one of said ternary digits of said multiplier input;
- first logic means associated with each of said programmable shift paths and including controllable XOR gates which form the ones complement of said associated multiplicand input when the sign of the associated ternary digit is negative;
- second logic means associated with each of said programmable shift paths and including controllable AND gates which force outputs of said XOR gates in said associated path to be set to zero when the associated ternary digit is zero;
- third logic means associated with each of said programmable shift paths and including controllable multiplexers which shift outputs of the AND gates according to the binary weighting of the associated ternary digit;
- and
- output means associated with each programmable shift path for providing a partial product output of the multiplicand and multiplier input associated with said path.
5 more elements
A method for FIR filtering a digital signal comprising:
- receiving a plurality of digital samples of said digital signal, each sample having a plurality of bits;
- providing time delays between each of said digital samples;
- summing selected pairs of said delayed samples;
- programming a plurality of programmable canonic signed digit (CSD) multipliers with a filter coefficient having weighted signed digits;
- multiplying each of said summed delayed samples in the plurality of programmable canonic signed digit (CSD) multipliers with each of said weighted canonic signed digits in separate multiplier shift paths to generate partial product outputs, wherein said multiplication is accomplished by first forming a ones complement of the summed delayed sample by inverting said bits;
- and
- adding the partial product outputs of said CSD multipliers and a summation of weighted carry-in bits for producing a twos complement inversion of each partial product for which the ones complement was previously formed to thereby provide a filter response.
4 more elements
Dependencies are inferred from the claim text.