Method and apparatus for optimizing complex arithmetic units for trivial operands
AssigneeSun Microsystems, Inc.
InventorStephen Richardson
Life of this patent
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Abstract
When an arithmetic operation is to be performed, the operands are concurrently sent to the arithmetic unit to perform the complex arithmetic operation and into an operand check mechanism which determines whether one or both of the operands is a specific instance of a trivial operand. If one of the operands is a specific instance of a trivial operand, the complex arithmetic operations are halted and the check mechanism rapidly outputs the result of the arithmetic operation according to the trivial operand detected. Consequently, the need to perform complex arithmetic operations on trivial operands is avoided.
Claims20
An optimization apparatus for performing arithmetic operations on one or more operands, said optimization apparatus comprising:
- an arithmetic unit including halt means for performing complex arithmetic operations, one or more operands being input to said arithmetic unit for each arithmetic operation being performed, said arithmetic unit generating a result for the arithmetic operation unless terminated by said halt means;
- detection means coupled to said arithmetic unit for detecting the existence of a trivial operand, said detection means coupled to receive one or more operands for the arithmetic operation to be performed concurrently with the arithmetic unit, said detection means generating an enabling signal identifying a trivial operand when a trivial operand is detected;
- trivial operand result means coupled to the detection means for generating the result of the arithmetic operation when at least one of the operands is a trivial operand, said trivial operand result means receiving said signal identifying a trivial operand and generating the result of the arithmetic operation based on said trivial operand identified;
- and
- arithmetic control means coupled to the detection means and to the arithmetic unit, said arithmetic control means issuing a halt signal to halt the arithmetic unit from performing the arithmetic operation when a trivial operand is detected;
- whereby a result for the arithmetic operation is generated without the need to perform the arithmetic operation in the arithmetic unit when at least one of the operands is a trivial operand.
A method for optimizing arithmetic operations performed by an arithmetic unit, said method comprising the steps of:
- providing an arithmetic unit including halt means for performing complex arithmetic operations;
- providing one or more operands to said arithmetic unit for each arithmetic operation being performed so that said arithmetic unit generates a result for the arithmetic operation unless terminated by said halt means;
- detecting the existence of a trivial operand from one or more operands input to said arithmetic unit by comparing said operands input to trivial operands;
- generating an enabling signal identifying a trivial operand when a trivial operand is detected;
- generating the result of the arithmetic operation based on said enabling signal when at least one of the operands is a trivial operand;
- and
- issuing a halt signal to halt the arithmetic unit from performing the arithmetic operation when a trivial operand is detected,
- whereby a result for the arithmetic operation is generated without the need to perform the arithmetic operation in the arithmetic unit when at least one of the operands is a trivial operand.
An optimization apparatus for performing arithmetic operations on one or more operands, said optimization apparatus comprising:
- an arithmetic unit including a halt function for performing complex arithmetic operations, one or more operands being input to said arithmetic unit for each arithmetic operation being performed, said arithmetic unit generating a result for the arithmetic operation unless terminated by said halt function;
- a plurality of comparators coupled to said arithmetic unit for detecting the existence of a trivial operand, said plurality of comparators coupled to receive one or more operands for the arithmetic operation to be performed concurrently with the arithmetic unit, said plurality of comparators generating an enabling signal identifying a trivial operand and issuing a halt signal to halt the arithmetic unit from performing the arithmetic operation when a trivial operand is detected;
- and
- a plurality of trivial operand registers coupled to the comparators for generating the result of the arithmetic operation when at least one of the operands is a trivial operand, said plurality of trivial operand registers receiving said signal identifying a trivial operand and generating the result of the arithmetic operation based on said trivial operand identified,
- whereby a result for the arithmetic operation is generated without the need to perform the arithmetic operation in the arithmetic unit when at least one of the operands is a trivial operand.
Dependencies are inferred from the claim text.