Circuit and method of switching between redundant clocks for a phase lock loop

A method of selecting between first and second input clock signals applied to a phase lock loop (PLL), comprising the steps of:

• checking validity of the first input clock signal and locking the PLL to the first input clock signal if valid;
• switching to the second input clock signal if the first input clock signal becomes invalid;
• checking the validity of the second input clock signal and locking the PLL to the second input clock signal if valid;
• applying a reference clock signal to the PLL during system reset for establishing a nominal operating point thereof;
• returning control of the PLL to said reference clock signal if both the first and second input clock signals are invalid;
• disabling movement of the PLL upon detecting an invalid state of the first input clock signal;
• checking the validity of the first input clock signal during a time period to see if it recovers;
• and
• returning control of the PLL to the first input clock signal if it recovers during said time period such that the PLL is still operating at substantially the frequency as before the failure of the first input clock signal.

A method of selecting between first and second input clock signals applied to a phase lock loop (PLL), comprising the steps of:

• checking validity of the first input clock signal by determining duration of a period of the first input clock signal and locking the PLL to the first input clock signal if valid;
• switching to the second input clock signal if the first input clock signal becomes invalid;
• and
• checking validity of the second input clock signal by determining duration of a period of the second input clock signal and locking the PLL to the second input clock signal if valid by,
• (a) disabling movement of the PLL upon detecting an invalid state of the second input clock signal,
• (b) checking the validity of the second input clock signal during a time period to see if it recovers, and
• (c) returning control of the PLL to the second input clock signal if it recovers during said time period such that the PLL is still operating at substantially the frequency as before the failure of the second input clock signal.

A phase lock loop (PLL), comprising:

• first means for comparing the phase of first and second digital input signals and generating an output signal to charge and discharge a loop node;
• a voltage controlled oscillator having an input coupled for receiving said output signal of said first means and providing a oscillator signal operating at a frequency as determined by said output signal of said first means;
• second means having an input coupled for receiving said oscillator signal from said voltage controlled oscillator and dividing down the frequency thereof for providing a first divided-down signal which is applied as said second digital input signal to said first means;
• a first multiplexer circuit responsive to first and second control signals for selecting between first and second input clock signals respectively applied at first and second inputs thereof for providing said first digital input signal to said first means at an output;
• and
• third means for monitoring validity of said first and second input clock signals by determining duration of a period of the first input clock signal and by determining duration of a period of the second input clock signal, said third means activating said first control signal when said first input clock signal is valid and activating said second control signal when said first input clock signal is invalid.