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US 5,258,986 AGranted
Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
AssigneeVLSI Technology, Inc.
InventorJared L. Zerbe
Life of this patent
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Abstract
RAM Built-In Self-Test logic is presented that utilizes a linear feedback shift register (LFSR) to generate data. Preferably, an LFSR is also utilized for address generation during memory self-testing. More than one cycle is implemented with offset of successive data sequences relative to address sequences to increase fault coverage. Memory storage is utilized in the data generation to enable a reduced area of the data generation circuitry.
Claims29
A method of testing memory having a set of M memory locations, said method comprising the steps of:
- (a) generating a first sequence F.sub.k that is pseudorandom;
- (b) generating a second sequence S.sub.k ;
- one of said first and second sequences is utilized as an address sequence A.sub.k and the other of said first and second sequences is utilized as a data sequence D.sub.k ;
- (c) for k=1 to some integer N, storing a kth data word D.sub.k in a memory location at address A.sub.k ;
- (d) for a sequence of values of k=1 to some integer L, comparing a value of data actually stored in the memory location at address A.sub.k with a value of the data word D.sub.k that was to be stored there to determine if there has been an error in storing this data word in this memory location;
- (e) generating a third sequence T.sub.k that is pseudorandom;
- and
- repeating steps (c) and (d) with third sequence T.sub.k in place of first sequence F.sub.k.
5 more elements
A memory having built-in self-test logic, said memory comprising:
- a memory core having M memory locations;
- means for generating a first sequence F.sub.k that is pseudorandom, a second sequence S.sub.k and a third sequence T.sub.k that is pseudorandom;
- one of the first and second sequences functions as an address sequence A.sub.k and the other functions as a data sequence D.sub.k ;
- means, for each value of k=1, . . . , M, for storing the kth data element D.sub.k in a location in said memory core at address A.sub.k determined from the first and second sequences and also for storing the kth data element D.sub.k in a location in said memory core at address A.sub.k determined from said second and third sequences;
- and
- means for comparing expected values in said memory core with actual values stored in this memory core.
3 more elements
Dependencies are inferred from the claim text.