Timing control for PRML class IV sampling data detection channel
AssigneeQuantum Corporation
InventorsKenneth E. Johnson, William L. Abbott, Hung C. Nguyen
Life of this patent
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Abstract
A multi-mode timing loop for a PR4,ML sampled data channel includes an analog to digital converter and a digital finite impulse response filter for providing conditioned digital samples. The timing loop includes a reference clock source for putting out a reference clock frequency related to a nominal sample data rate, a frequency controllable oscillator connected to generate a sample clock, an analog timing loop and a digital timing loop. The analog timing loop provides phase lock during non-data read mode, and during data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting then provided by the analog timing loop.
Claims15
A multi-mode timing loop for a PR4,ML sampled data channel including an analog to digital sampling and conversion means for providing raw digital samples of data at a sample clock rate and a digital finite impulse response filter means connected downstream of said analog to digital sampling and conversion means for providing conditioned digital samples at the sample clock rate, said timing loop comprising:
- reference clock source means for putting out a reference clock frequency related to a nominal sample clock rate for sampling data in said channel,
- controllable oscillator means for putting out a sample clock,
- an analog timing loop including:
- phase detector means for detecting and putting out a phase error between said reference clock frequency and said sample clock,
- charge pump means connected to receive said phase error and pump charge during a non-data read mode of operation of said multi-mode timing, loop,
- analog loop filter and charge storage means connected to receive charge pumped by said charge pump means during a non-data read mode and to filter and hold said charge during a data read mode of operation, said analog loop filter for putting out an analog timing control value to said controllable oscillator means,
- a digital timing loop including:
- timing error extraction means connected to receive said digital samples from said finite impulse response filter means for extracting timing error values therefrom,
- digital timing loop filter means for filtering said timing error values, and
- timing digital to analog converter means for converting said filtered timing error values into analog vernier timing correction values and for supplying said analog vernier timing correction values to said frequency controllable oscillator means during the data read mode,
- whereby the analog timing loop provides phase lock during non-data read mode and wherein during the data read mode the digital timing loop provides a vernier offset for fine adjustment of phase lock to a static setting provided by said analog timing loop at said frequency controllable oscillator means.
A method for timing a PR4,ML sampled data channel including an analog to digital sampling and conversion means for providing raw digital samples of data at a sample clock rate and a digital finite impulse response filter means connected downstream of said analog to digital sampling and conversion means for providing conditioned digital samples at the sample clock rate, said timing method comprising the steps of:
- putting out a reference clock frequency related to a nominal sample clock rate for sampling data in said channel,
- generating and putting out a sample clock,
- detecting and putting out an analog phase error between said reference clock frequency and said sample clock,
- charging a storing means with a charge related to said phase error during a non-data read mode,
- filtering and converting said charge into an analog timing control value and applying said analog timing control value to control the frequency of said sample clock during the non-data read mode and during a data read mode,
- receiving said digital samples from said finite impulse response filter means and extracting timing error values therefrom,
- filtering said timing error values, and
- converting said filtered timing error values into analog vernier timing correction values and supplying said analog vernier timing correction values to adjust the frequency of said sample clock during the data read mode.
Dependencies are inferred from the claim text.