Phase-locked loop circuit and method

A phase-locked loop circuit for providing an output signal which is phase locked with respect to an input signal, said phase-locked loop circuit comprising:

• phase detector means for producing a detector output indicative of a difference in phase between the input and output signals;
• controlled oscillator means for producing an oscillator output signal in response to the detector output signal;
• frequency divider means for dividing the frequency of the oscillator output signal by a variable value to produce the output signal;
• and
• control means for determining the frequency divider means variable value based upon the frequency of the input signal and independent of the phase detector means.

A phase-locked loop circuit for providing an output signal which is phase locked with respect to an input signal, said phase-locked loop circuit comprising:

• phase detector means for producing a detector output indicative of a difference in phase between the input and output signals;
• controlled oscillator means for producing an oscillator output signal in response to the detector output signal, with the output signal having a plurality of different operating frequencies selected in response to a control signal separate from the detector output signal;
• and
• control means for producing the control signal in response to the frequency of the input signal and independent of the phase of the input signal.

A method of producing an output signal which is phased locked to an input signal comprising the following steps:

• selecting one of a plurality of frequency operating bands based upon the frequency of the input signal and independent of the phase of the input signal;
• generating the output signal in the selected frequency operating band;
• comparing the phase relationship between the generated output signal and the input signal;
• and
• controlling the phase of the generated output signal based upon the step of comparing.