Fault tolerant, synchronized twin computer system with error checking of I/O communication

A dual processor computer system for connection to at least one input/output device comprising:

• a first processing system including
• a first central processing unit executing a series of data processing instructions including I/O instructions,
• a first dedicated bus coupled to said first central processing unit;
• a first memory unit coupled to said first central processing unit by said first dedicated bus,
• first communications means coupled to said first central processing unit for transferring data into and out of said first processing system;
• and
• a first data bus system coupled to said first communication means to transfer data to and from said first communication means;
• a second processing system, operating independently of said first processing system, said second processing system including
• a second central processing unit executing said series of data processing instructions including I/O instructions in the same order and approximately synchronously with said first central processing unit such that each of the instructions in said series of data processing instructions is executed approximately simultaneously by said first and second processing systems,
• a second dedicated bus coupled to said second central processing unit;
• a second memory unit coupled to said second central processing unit by said second dedicated bus, and
• second communications means, coupled to said second central processing unit and to said first communications means, for transferring data into and out of said second processing system;
• a second data bus system coupled to said second communications means for transferring data into and from said second communication means;
• and
• checking means, coupled to said first and second data bus systems, for comparing the data transferred out of said first and second processing systems by said first and second communications means, to said at least one input/output device during the approximately synchronous execution of said series of data processing instructions by said first and second processing systems in response to said I/O instructions to determine correct instruction execution by said first and second processing systems.