One stage word line decoder/driver with speed-up Darlington drive and adjustable pull down

Abstract

A word line decoder/driver has a Darlington circuit connected in parallel with word line driver transistors to provide rapid switching thereof. The Darlington circuit receives an input from decoder transistors through a capacitance, such as a diffusion capacitance, which establishes a time constant longer than the nominal access cycle time of the memory. Thus, during the nominal cycle time of the memory, the word line driver transistors merely supplement the pull-up of the word lines, the speed of which is limited only by the switching speed of the Darlington circuit. Therefore, the pull-up of the input to the word line driver transistors is made non-critical and the circuit can be simplified to reduce element count while achieving substantial reduction in power consumption. While the fast collector pull down of the deselected word line is controlled by an adjustable clamp, word line pull-up is maintained well below 1 nsec and chip access time is below 2 nsec and voltage margins are increased. By converting input voltage levels to lower values with respect to the power supply voltage, large voltage swings can be achieved with a single stage circuit within a 3.6 volt power supply.

Dependencies are inferred from the claim text.