Bidirectional first-in-first-out memory device with transparent and user-testable capabilities

A bi-directional first-in-first-out (FIFO) memory device on a monolithic integrated circuit chip, comprising:

• first and second device input/output (I/O) ports;
• a single FIFO memory array for holding the FIFO data no matter which direction data is transferred through said FIFO device, said array comprising an input data port and an output data port;
• means responsive to a first control signal for selectively coupling either said first or said second device I/O port to said input data port of said memory array;
• means responsive to a second control signal for selectively coupling either said first or said second device I/O port to said output data port of said memory array, whereby said FIFO device may be operated for data transfer either from said first I/O port to said second I/O port or vice versa in dependence on the setting of said means responsive to said first control signal and said means responsive to said second control signal;
• means responsive to transparent bypass control signals for operating said device in a transparent bypass mode of operation, wherein data asserted at one of said first and second ports bypasses said FIFO memory array and is transferred directly to said other of said first and second ports without passing through said FIFO memory array;
• and
• means responsive to registered bypass control signals for operating said device in a registered bypass mode of operation, wherein data may be transferred via a clocked register from one I/O port for later retrieval by the other I/O port without affecting either the contents of the FIFO memory array or FIFO operations occurring at the other I/O port.

A user-testable first-in-first-out (FIFO) memory device on a monolithic integrated circuit chip, comprising:

• first and second device data ports, said first device data port comprising means for inputting data into said FIFO device during normal operation of said FIFO device, said second device data port comprising means for outputting data from said FIFO device during normal operation of said FIFO device, and wherein during a device test mode data may be read out of said FIFO device;
• a FIFO memory array having an input data port and an output data port;
• first means for coupling data from said first device data port to said input data port of said FIFO memory array to write data into said array during normal device operations;
• second means for coupling data from said output data port of said FIFO memory array to said first device data port during normal device operations, wherein data is available at said second device data port in the same order it was presented to the first device data port;
• and
• third means for coupling data from said output data port of said FIFO memory array to said first device data port during a test mode of operation of said device.

A method of integrated circuit device mode selection, comprising a sequence of the following steps:

• observing the state of first and second predetermined device control pins;
• starting a predetermined "time out" time interval in the event said state of said first pin transitions to a predetermined state;
• selecting a first device mode if said second device control pin transitions to a predetermined state before expiration of said "time out" interval;
• selecting a second device mode if said second device control pin does not transition to said predetermined state before expiration of said "time out" interval.

A bi-directional first-in-first-out (FIFO) memory device on a monolithic integrated circuit chip, comprising:

• first and second device input/output (I/O) ports;
• a single FIFO memory array for holding the FIFO data no matter which direction data is transferred through said FIFO device, said array comprising an input data port and an output data port;
• means responsive to a first control signal for selectively coupling either said first or said second device I/O port to said input data port of said memory array;
• means responsive to a second control signal for selectively coupling either said first or said second device I/O port to said at least one output data port of said memory array;
• and
• means responsive to registered bypass control signals for operating said device in a registered bypass mode of operation, wherein data may be transferred via a clocked register from one I/O port for later retrieval by the other I/O port without affecting either the contents of the FIFO memory array or FIFO operations occurring at the other I/O port, and wherein the direction of registered bypass data is opposite to that of the selected FIFO data transfer operation through the device;
• whereby said FIFO device may be operated for data transfer either from said first I/O port to said second I/O port or vice versa depending upon the setting of said means responsive to said first control signal and said means responsive to said second control signal, enabling data transfer from said first I/O port to said second I/O port when said first I/O port is coupled to said input data port of said memory and said second I/O port is coupled to said output data port for said device, and enabling data transfer from said second I/O port to said first I/O port when said second I/O port is coupled to said input data port and said first I/O port is coupled to said output data port.

A bi-directional first-in-first-out (FIFO) memory device on a monolithic integrated circuit chip, comprising:

• first and second device input/output (I/O) ports;
• a single FIFO memory array for holding the FIFO data no matter which direction data is transferred through said FIFO device, said array comprising an input data port and an output data port;
• means responsive to a first control signal for selectively coupling either said first or said second device I/O port to said input data port of said memory array;
• means responsive to a second control signal for selectively coupling either said first or said second device I/O port to said at least one output data port of said memory array;
• and
• means operable during a device testing mode for reading data written into said FIFO memory array out of said device I/O port through which said data was written;
• whereby said FIFO device may be operated for data transfer either from said first I/O port to said second I/O port or vice versa depending upon the setting of said means responsive to said first control signal and said means responsive to said second control signal, enabling data transfer from said first I/O port to said second I/O port when said first I/O port is coupled to said input data port of said memory and said second I/O port is coupled to said output data port for said device, and enabling data transfer from said second I/O port to said first I/O port when said second I/O port is coupled to said input data port and said first I/O port is coupled to said output data port.