Advanced phase locked loop circuit

A PLL circuit comprising:

• a voltage controlled oscillator responsive to a control signal to output an output signal having a variable oscillation frequency;
• a phase detector for making a phase comparison between the output signal from said voltage controlled oscillator and a reference signal, and for outputting an output error signal;
• an integrator for integrating the output error signal from said phase detector to extract a direct current variable component contained in the output error signal, said integrator having a first cutoff frequency;
• a loop filter for feeding the direct current variable component from said integrator to said voltage controlled oscillator as the control signal to synchronize the output signal from said voltage controlled oscillator with the reference signal;
• an alternate current coupling for adding only an alternate current component contained in the output error signal from said phase detector to the control signal for feeding to said voltage controlled oscillator;
• and
• a compensating circuit inserting in an alternate current signal path of said alternate current coupling circuit, said compensating circuit having a second cutoff frequency exceeding the first cutoff frequency of said integrator.

A PLL circuit having a frequency detection function, said circuit comprising:

• a voltage controlled oscillator;
• a phase detector for detecting a phase difference between a first reference signal and an output signal from said voltage controlled oscillator, and for outputting an error voltage according to the phase difference;
• a loop filter for integrating the error voltage from said phase detector and for controlling said voltage controlled oscillator;
• a control section for outputting upper limit frequency information and lower limit frequency information according to desired frequency setting information;
• a first frequency comparator for dividing the frequency of the output signal from said voltage controlled oscillator according to the upper limit frequency information, comparing frequencies of a second reference signal and a frequency-divided signal and outputting down-pulses when the frequency of the frequency-divided signal is higher than that of the second reference signal;
• a second frequency comparator for dividing the frequency of the output signal from said voltage controlled oscillator according to the lower limit frequency information, comparing frequencies of the second reference signal and a frequency-divided signal and outputting up-pulses when the frequency of the frequency divided signal is lower than that of the second reference signal;
• and
• an up-down processor for receiving and inputting the down-pulses and the up-pulses to an input section of said loop filter to add to the error voltage from said phase detector;
• wherein said loop filter comprises:
• a first amplifier responsive to the error voltage added to one of the up-pulses and the down-pulses, for determining a response characteristic of said loop filter together with a lag-lead filter;
• a second amplifier, responsive to an output from the first amplifier, for inputting the error voltage with a predetermined phase to said voltage controlled oscillator;
• and
• a notch filter, responsive to an output from the second amplifier, for removing a fixed frequency component contained in the error voltage;
• said lag-lead filter receiving outputs from said second amplifier and said notch filter and supplying a control voltage to said voltage controlled oscillator;
• whereby to perform the frequency detecting function for tracking the frequency of the output signal from said voltage controlled oscillator within a predetermined frequency range determined by the upper and lower limit frequency information and pulling in the frequency of the first reference signal.