Massively parallel digital image data processor using pixel-mapped input/output and relative indexed addressing

An image processing system for processing image data provided by an external image sensor which provides digital image data having a predetermined number of bits of data, said processing system comprising:

• a plurality of interconnected processing elements for receiving and processing said digital image data to provide processed digital image data, said plurality of processing elements being electrically configured in a two-dimensional matrix, said matrix comprising a plurality of rows and a plurality of columns in which a processing element is electrically located at the intersection of each row and each column, each of said processing elements having an address corresponding to the respective row and column in which each processing element lies;
• first bussing means, coupled to said processing elements for receiving said digital image data from said sensor and routing said digital image data to said processing elements;
• second bussing means, coupled to said processing elements for routing said processed digital image data from said processing elements;
• and
• controller means for controlling said routing of said digital image data to and from said processing elements along said first and second bussing means and for controlling said processing elements and for directly and randomly accessing image data in said processing elements, said controller means including a memory having a plurality of address locations, wherein said address locations correspond to said addresses of said processing elements, such that said addresses of said processing elements are memory-mapped into said controller means.

An image processing system for processing digital image data having a predetermined number of bits of data corresponding to an image having a plurality of pixels arranged in a matrix, said processing system comprising:

• a plurality of interconnected processing elements for receiving and processing said digital image data, said plurality of processing elements being electrically configured in an array;
• data transfer means for transmitting data to and receiving data from other processing elements within said plurality of processing elements;
• first bussing means, coupled to said processing elements for receiving said digital image data and routing said digital image data to said processing elements;
• second bussing means, coupled to said processing elements for routing said processed digital image data from said processing elements;
• and
• controller means for controlling said routing of said digital image data to and from said processing elements along said first and second bussing means and for controlling said processing elements, said control of said processing elements comprising controlling accessing of image data corresponding to a target pixel stored in a first one of said processing elements and instructing a second of said processing elements to receive and process the target pixel image data from said first one of said processing elements, based upon a relative indexed address, wherein said relative indexed address corresponds to the number of rows and number of columns of said matrix separating said base pixel in said second processing element receiving said image data from said target pixel in said first processing element from which said image data is to be received.

An image processing system for processing image data provided by an external image sensor which provides digital image data having a predetermined number of bits of data, said processing system comprising:

• a plurality of interconnected processing elements for receiving and processing said digital image data, said plurality of processing elements being electrically configured in a two-dimensional matrix comprising a plurality of rows and a plurality of columns in which a processing element is electrically located at the intersection of each row and each column and the respective address for each of said processing elements corresponds to the respective row and column in which each processing element lies, each processing element including a relative address generator circuit comprising:
• first instruction reception means for receiving first microcode instructions indicative of, a relative digital memory location being relative to a reference digital memory location, said digital memory locations each containing a plurality of digital bits therein;
• first decoding means for decoding said first microcode instructions into said relative address data, said relative address data being representative of a relative digital memory location;
• second instruction reception means for receiving second microcode instructions indicative of bit data, said bit data being representative of a digital bit located within said relative digital memory location;
• first address data reception means for receiving direct address data, said direct address data being representative of said digital bit;
• first selection means for selecting a range of possible values for said relative address data;
• second selection means for selecting a number of said digital bits to be represented by said bit data;
• combination means for combining said relative address data with said bit data to create relative indexed address data;
• and
• third selection means for selecting between said relative indexed address data and said direct address data;
• and
• controller means for controlling routing of said digital image data to and from said processing elements and for controlling said processing elements, said control of said processing elements comprising provision of first and second microcode instructions and first address data to said processing elements when instructing said processing elements to receive and process image data from other processing elements.

An image processing method for processing digital image data having a predetermined number of bits of data corresponding to the pixels of an image having a matrix of pixels by a plurality of processing elements electrically configured and interconnected in a two-dimensional array, said pixel matrix having a plurality of rows and a plurality of columns, said processing method comprising the steps of:

• routing said digital image data to said plurality of processing elements;
• selectively storing said digital image data associatively with respect to said processing elements;
• accessing and acquiring, by a first processing element, digital image data corresponding to a target pixel initially stored associatively with respect to a second processing element, said first processing element accessing said digital image data by specifying the relative location of said target pixel relative to the location of base pixel in said first processing element within said matrix of pixels, said relative location corresponding to the number of said rows and number of said columns separating said target pixel and base pixel;
• processing said accessed and acquired digital image data arithmetically and logically, selectably, within said processing elements;
• and
• routing said processed digital image data out from said plurality of processing elements.