Switching system with time-stamped packet distribution input stage and packet sequencing output stage

A packet switching system having a plurality of input ports and a plurality of output ports, comprising:

• a plurality of packet distributors associated respectively with the input ports for receiving successive packets therefrom at a data rate V, each of said packet distributors attaching a timeslot number to each of the received packets, and uniformly distributing the packets to a plurality of output terminals thereof, so that the packets appear at each of the output terminals at a data rate V/N, where N is the number of said output terminals of each of the packet distributors;
• a plurality of packet switches corresponding in number to the output terminals of each of the packet distributors, each of the packet switches having a plurality of input terminals corresponding in number to the packet distributors and a plurality of output terminals corresponding in number to said output ports, the input terminals of each of the packet switches being coupled to respective output terminals of said packet distributors for switching a packet from one of the input terminals thereof to one of the output terminals thereof in accordance with a destination address contained in the packet;
• and
• a plurality of packet sequencers associated respectively with said output ports, each of the packet sequencers having a plurality of input terminals coupled to respective output terminals of the packet switches for examining the timeslot numbers attached to the packets from the input terminals thereof and delivering the packets to the associated output port in accordance with the examined timeslot numbers.