US 5,251,097 AGranted

Packaging architecture for a highly parallel multiprocessor system

AssigneeSupercomputer Systems Limited Partnership

InventorsFrederick J. Simmons, Steve S. Chen, Greg W. Pautsch, Michael H. Rabska, Dennis F. Girling, Douglas C. Paffel, Dan L. Massopust, Lisa Heid, Felix R. Lesmerises, Christopher J. Sperry, Edward C. Priest

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Abstract

The present invention includes methods and apparatus for creating a packaging architecture for a highly parallel multiprocessor system. The packaging architecture of the present invention can provide for distribution of power, cooling and interconnections at all levels of components in a highly parallel multiprocessor system, while maximizing the number of circuits per unit time within certain operational constraints of such a multiprocessor system.

Claims13

Dependent claims

An apparatus for packaging circuitry means for a computer processing system, said apparatus comprising:

a first substrate and a second substrate spaced apart from said first substrate, said first and second substrates each comprising a generally planar structure including:
a first substrate area having a plurality of circuitry elements and a plurality of backplane external interconnections operably connected to said first substrate area and means for providing a plurality of signal paths to and from said circuitry elements and to and from said backplane external interconnections:
and
a second substrate area having a plurality of circuitry elements operably connected to said second substrate area and means for providing a plurality of signal paths to and from said circuitry elements;
and
transformation board means intersecting said first and second substrates for providing a plurality of signal paths for connecting said signal paths between said first and second substrate areas and between said first and second substrates,
such that the intersection of said transformation board means with said first and second substrates defines a planar boundary between said first and second substrate area on each of said first and second substrates and the only connections to and from said circuitry elements on said second substrate areas are via said signal paths on said transformation board means to said signal paths and said backplane external interconnections on said first substrate areas.

4 more elements

A packaging architecture for a multiprocessor cluster for a highly parallel computer processing system, said multiprocessor cluster comprising shared resource means for storing and retrieving data and control information, a plurality of processors capable of parallel processing, and one or more arbitration node means operably connected to said processors and said shared resource means for symmetrically interconnecting said processors with said shared resource means, said packaging architecture comprising:

a plurality of modular brick means for packaging a portion of electronic circuitry for said computer processing system, each brick means comprising:
switching circuit means for controlling the routing of signals to and from said brick means operably connected to a plurality of spaced apart first substrates;
functional circuit means for performing functional operations operably connected to a plurality of spaced apart second substrates, each of said second substrates being associated with one of said first substrates;
and
transformation board means intersecting each of said plurality of first and second substrates for providing a plurality of signal paths to interconnect said switching circuit means and said functional circuit means;
and
a plurality of columns, each column comprised of two or more of said brick means operably connected together.

4 more elements

Dependencies are inferred from the claim text.