Back to results
US 5,250,860 AGranted
Three-level cascode differential current switch
AssigneeInternational Business Machines Corporation
InventorsWilliam M.-S. Chu, Carl K.-L. Wong
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeInternational Business Machines Corporation
InventorsWilliam M.-S. Chu, Carl K.-L. Wong
Estimating the term…
A three-level input voltage level conversion circuit for three-level emitter coupled logic (ECL) cascode circuit provides three unique input levels. The input voltage level conversion circuit has a level shift up circuit for the top level input, a direct input to the middle level input, and a conventional emitter follower input for the bottom level input. The shift up circuit consists of a differential pair with differential inputs to the bases of each transistor. The collectors of these transistors are coupled to the upper level of the three-level cascode logic circuit. The emitters of the differential pair are coupled to the collector of a current source transistor. The base of the current source transistor is connected to an activation potential, and the emitter is coupled through a resistor to a reference potential. The down shift is accomplished with a differential transistor pair with bases directly coupled to a differential input pair. The collectors of these transistors are coupled to a positive potential and the emitters are coupled through resistors to a reference potential. The emitters are the differential output of the circuit and are directly coupled to the lower level of the cascode circuit.
Input voltage level conversion circuitry for three-level cascode logic circuits, said three-level cascode logic circuits having an upper level, middle level and lower level connected in a tree structure, a first standard current source connected to a base of said tree structure and each of said levels receiving respective differential inputs, said input circuitry comprising an upper level stage comprising an upshift circuit having a second standard current source identical to said first standard current source and translating a voltage level of a first pair of differential inputs to a higher level and connecting the translated voltage level to the upper level of one or more of said three-level cascode logic circuits, a middle level stage connecting a second pair of differential inputs directly connected to the middle level of one or more of said three-level cascode logic circuits, and a lower level stage comprising a downshift circuit translating a voltage level of a third pair of differential inputs to a lower level and connecting the translated voltage level to the lower level of one or more of said three-level cascode logic circuits.
A three-level cascode Exclusive OR logic circuit having an upper level, middle level and lower level connected in a tree structure, a first standard current source connected to a base of said tree structure and each of said levels receiving respective differential inputs, and input circuitry comprising an upper level stage comprising an upshift circuit having a second standard current source identical to said first standard current source and translating a voltage level of a first pair of differential inputs to a higher level and connecting the translated voltage level to the upper level of said three-level cascode Exclusive OR logic circuit, a middle level stage connecting a second pair of differential inputs directly connected to the middle level of said three-level cascode Exclusive OR logic circuit, and a lower level stage comprising a downshift circuit translating a voltage level of a third pair of differential inputs to a lower level and connecting the translated voltage level to the lower level of said three-level cascode Exclusive OR logic circuit.
A full adder circuit comprising a three-level cascode Exclusive OR logic circuit and a three-level cascode AND-OR logic circuit each having an upper level, middle level and lower level connected in a tree structure, a first standard current source connected to a base of said tree structure and each of said levels receiving respective differential inputs, and input circuitry comprising an upper level stage comprising an upshift circuit having a second standard current source identical to said first standard current source and translating a voltage level of a first pair of differential inputs to a higher level and connecting the translated voltage level to the upper level of each of said three-level cascode Exclusive OR and AND-OR logic circuits, a middle level stage connecting a second pair of differential inputs directly connected to the middle level of each of said three-level cascode Exclusive OR and AND-OR logic circuits, and a lower level stage comprising a downshift circuit translating a voltage level of a third pair of differential inputs to a lower level and connecting the translated voltage level to the lower level of each of said three-level cascode Exclusive OR and AND-OR logic circuits.
Dependencies are inferred from the claim text.