Buffer memory data flow controller

A buffer memory data flow controller, coupled to a microprocessor, a buffer controller, a buffer memory, an interface processor, and input/output device controller, for controlling the transfer of data between the interface and the input/output device controller, the data flow controller comprising:

• a. a counter including validation means for generating a validation signal when the amount of data in the buffer memory equals a preset comparison value;
• b. counter control means, coupled to the counter, for changing the count value of the counter to indicate an increase of data when data is transferred into the buffer memory, and for changing the count value of the counter to indicate a decrease of data when data is transferred out of the buffer memory;
• c. pause signal generation means, coupled to the counter and the counter control means, for:
• (1) generating an interface pause signal when the buffer memory is full during a transfer of data from the interface processor to the input/output device controller, or when the buffer memory is empty during a transfer of data from the input/output device controller to the interface processor;
• and
• (2) generating an input/output device controller pause signal when the buffer memory is empty during a transfer of data from the interface processor to the input/output device controller, or when the buffer memory is full during a transfer of data from the input/output device controller to the interface processor;
• wherein data is transferred between the interface processor and the input/output device controller only when the amount of data in the buffer memory at least equals the preset comparison value while the data flow control means is operating;
• and
• wherein data is not transferred between the interface processor and the buffer memory if the interface pause signal is generated, and data is not transferred between the input/output device controller and the buffer memory if the input/output device pause signal is generated.

A buffer memory data flow controller system comprising:

• a. microprocessor means for controlling the operation of the buffer memory data flow controller system;
• b. buffer memory means for storing data;
• c. buffer controller means, coupled to the microprocessor means and the buffer memory means, for controlling writing of data into and reading data out of the buffer memory means;
• d. interface means, coupled to the microprocessor means, a data bus, and the buffer controller means, for controllably transmitting data between the data bus and the buffer memory means through the buffer controller means;
• e. input/output device controller means, coupled to the microprocessor means, an input/output device, and the buffer controller means, for controllably transmitting data between the input/output device and the buffer memory means through the buffer controller means;
• f. data flow control means, coupled to the microprocessor means, the buffer controller means, the interface means, and the input/output device controller means, for controlling the transfer of data between the interface means and the input/output device controller means, the data flow control means comprising:
• (1) a counter including validation means for generating a validation signal when the amount of data in the buffer memory means equals a preset comparison value;
• (2) counter control means, coupled to the counter, for changing the count value of the counter to indicate an increase of data when data is transferred into the buffer memory means, and for changing the count value of the counter to indicate a decrease of data when data is transferred out of the buffer memory means;
• wherein data is transferred between the interface means and the input/output device controller means only when the amount of data in the buffer memory means at least equals the preset comparison value while the data flow control means is operating.

A buffer memory data flow controller system comprising:

• a. microprocessor means for controlling the operation of the buffer memory data flow controller system;
• b. buffer memory means for storing data;
• c. buffer controller means, coupled to the microprocessor means and the buffer memory means, for controlling writing of data into and reading data out of the buffer memory means;
• d. interface means, coupled to the microprocessor means, a data bus, and the buffer controller means, for controllably transmitting data between the data bus and the buffer memory means through the buffer controller means;
• e. input/output device controller means, coupled to the microprocessor means, an input/output device, and the buffer controller means, for controllably transmitting data between the input/output device and the buffer memory means through the buffer controller means;
• f. data flow control means, coupled to the microprocessor means, the buffer controller means, the interface means, and the input/output device controller means, for controlling the transfer of data between the interface means and the input/output device controller means, the data flow control means comprising:
• (1) a pre-settable counter including validation means for generating a validation signal when the amount of data in the buffer memory means equals a preset comparison value;
• (2) counter control means, coupled to the counter, for changing the count value of the counter to indicate an increase of data when data is transferred into the buffer memory means, and for changing the count value of the counter to indicate a decrease of data when data is transferred out of the buffer memory means;
• (3) comparison means, coupled to the counter, for indicating to the microprocessor means at least one of the conditions that the amount of data in the buffer memory means equals (1) an "almost empty" preset comparison value or (2) an "almost full" preset comparison value;
• (4) pause signal generation means, coupled to the counter and the counter control means,
• (a) for generating an interface pause signal when the buffer memory means is full during a transfer of data from the data bus to the input/output device, or when the buffer memory means is empty during a transfer of data from the input/output device to the data bus;
• (b) for generating a input/output device controller pause signal when the buffer memory means is empty during a transfer of data from the data bus to the input/output device, or when the buffer memory means is full during a transfer of data from the input/output device to the data bus;
• wherein data is transferred between the interface means and the input/output device controller means only when the amount of data in the buffer memory means at least equals the present comparison value while the data flow control means is operating;
• and
• wherein data is not transferred between the interface means and the buffer memory means if the interface pause signal is generated, and data is not transferred between the input/output device controller means and the buffer memory means if the input/output device pause signal is generated.

A method for controlling the transfer of data between a data bus and an input/output device through a buffer memory, the method comprising the steps of:

• a. keeping count of the amount of data in the buffer memory;
• b. changing the count value to indicate an increase of data when data is transferred into the buffer memory;
• c. changing the count value to indicate a decrease of data when data is transferred out of the buffer memory;
• d. generating a validation signal when the amount of data in the buffer memory equals a preset comparison value;
• e. generating an interface pause signal when the buffer memory is full during a transfer of data from the data bus to the input/output device, or when the buffer memory is empty during a transfer of data from the input/output device to the data bus;
• f. generating a input/output device controller pause signal when the buffer memory is empty during a transfer of data from the data bus to the input/output device, or when the buffer memory is full during a transfer of data from the input/output device to the data bus;
• g. enabling the transfer of data between the data bus and the input/output device only when the amount of data in the buffer memory at least equals the preset comparison value;
• and
• h. disabling data transfers between the data bus and the buffer memory if the interface pause signal is generated;
• i. disabling data transfers between the input/output device and the buffer memory if the input/output device pause signal is generated.

A method for controlling the transfer of data between a data bus and an input/output device through a buffer memory, the method comprising the steps of:

• a. changing the count value of a counter to indicate an increase of data when data is transferred into the buffer memory;
• b. changing the count value of a counter to indicate a decrease of data when data is transferred out of the buffer memory;
• c. generating a validation signal from the counter when the amount of data in the buffer memory equals a preset comparison value;
• d. generating an interface pause signal when the buffer memory is full during a transfer of data from the data bus to the input/output device, or when the buffer memory is empty during a transfer of data from the input/output device to the data bus;
• e. generating a input/output device controller pause signal when the buffer memory is empty during a transfer of data from the data bus to the input/output device, or when the buffer memory is full during a transfer of data from the input/output device to the data bus;
• f. enabling the transfer of data between the data bus and the input/output device only when the amount of data in the buffer memory at least equals the preset comparison value;
• and
• g. disabling data transfers between the data bus and the buffer memory if the interface pause signal is generated;
• h. disabling data transfers between the input/output device and the buffer memory if the input/output device pause signal is generated.

A buffer memory data flow controller system comprising:

• a. a microprocessor for controlling the operation of the buffer memory data flow controller system;
• b. a buffer memory for storing data;
• c. a buffer controller, coupled to the microprocessor and the buffer memory, for controlling writing of data into and reading data out of the buffer memory;
• d. a SCSI interface processor, coupled to the microprocessor, a SCSI data bus, and the buffer controller, for controllably transmitting data between the data bus and the buffer memory through the buffer controller;
• e. an input/output device controller, coupled to the microprocessor, an input/output device, and the buffer controller, for controllably transmitting data between the input/output device and the buffer memory through the buffer controller;
• f. a data flow controller, coupled to the microprocessor, the buffer controller, the SCSI interface processor, and the input/output device controller, for controlling the transfer of data between the SCSI interface processor and the input/output device controller, the data flow control comprising:
• (1) a pre-settable counter including validation means for generating a validation signal when the amount of data in the buffer memory equals a preset comparison value;
• (2) a counter controller, coupled to the counter, for changing the count value of the counter to indicate an increase of data when data is transferred into the buffer memory, and for changing the count value of the counter to indicate a decrease of data when data is transferred out of the buffer memory;
• (3) a comparator, coupled to the counter, for indicating to the microprocessor at least one of the conditions that the amount of data in the buffer memory equals (1) an "almost empty" preset comparison value or (2) an "almost full" preset comparison value;
• (4) a pause signal generator, coupled to the counter and the counter controller,
• (a) for generating an interface pause signal when the buffer memory is full during a transfer of data from the data bus to the input/output device, or when the buffer memory is empty during a transfer of data from the input/output device to the data bus;
• (b) for generating a input/output device controller pause signal when the buffer memory is empty during a transfer of data from the data bus to the input/output device, or when the buffer memory is full during a transfer of data from the input/output device to the data bus;
• wherein data is transferred between the SCSI interface processor and the input/output device controller only when the amount of data in the buffer memory at least equals the preset comparison value while the data flow control is operating;
• and
• wherein data is not transferred between the SCSI interface processor and the buffer memory if the interface pause signal is generated, and data is not transferred between the input/output device controller and the buffer memory if the input/output device pause signal is generated.

A method for controlling the transfer of data between a data bus and an input/output device through a buffer memory, the method comprising the steps of:

• a. changing the count value of a counter to indicate an increase of data when data is transferred into the buffer memory;
• b. changing the count value of a counter to indicate a decrease of data when data is transferred out of the buffer memory;
• c. generating a validation signal from the counter when the amount of data in the buffer memory equals a preset comparison value;
• d. determining at least one of the conditions that the amount of data in the buffer memory equals (1) an "almost empty" preset comparison value or (2) an "almost full" preset comparison value;
• e. enabling the transfer of data between the data bus and the input/output device only when the amount of data in the buffer memory at least equals the preset comparison value;
• and
• f. maintaining an essentially continuous flow of data between the interface processor and the input/output device controller in response to the "almost empty" or "almost full" conditions.