DCT/IDCT processor and data processing method

A processor having at least a function of carrying out one-dimensional inverse discrete cosine transform of N-term multibit input data Y, wherein said N is a positive integer, said processor comprising:

• matrix product means for dividing said N-term multibit input data Y into a first set of input data and a second set of input data and carrying out a product operation of said first set of input data and a first coefficient matrix and a product operation of said second set of input data and a second coefficient matrix, to generate a first set of intermediate data Mi and a second set of intermediate data Ni, wherein said i is an integer of 0.ltoreq.i.ltoreq.N/2-1;
• and
• postprocessing means for carrying out addition and substraction of two intermediate data in a predetermined relationship in said first set of intermediate data and said second set of intermediate data from said matrix product means to generate first and second sets of output data Xi;
• said matrix product means including
• storage means for sequentially receiving and storing said second set of data,
• first parallel reading means for reading, in parallel and in order, one-bit data in the same bit figure of all of said second set of data stored in said storage means, and
• means responsive to said first parallel reading means for producing said second set of intermediate data.

In a processor including storage means for sequentially receiving and storing first and second sets of data, first parallel reading means for reading in parallel and in order, one-dimensional data in the same bit figure of all of said first set of data stored in said storage means, second parallel reading means for reading in parallel and in order, one-bit data in the same bit figure of all of said second set of data stored in said storage means, and a ROM, storing in advance data indicating the result of product sums of a corresponding coefficient and parallel bit data in a table form, for receiving parallel bit data from said first and second parallel reading means as address signals to output a corresponding partial sum, a method of processing one dimensional discrete cosine transform of N points on input data X, wherein N is 2.sup.m with m being a natural number, comprising the steps of:

• carrying out addition and substraction of each 2-term data in predetermined relationship in said input data X to generate a first set of addition data and a second set of substraction data, said first and second sets including N/2-term data;
• accessing said ROM using said first set of N/2-term data as an address signal and outputting a corresponding partial sum as first output data;
• accessing said ROM using said second set of N/2-term data as an address signal and outputting a corresponding partial sum as second output data;
• and
• outputting said first and second sets of output data in a predetermined order.

In a processor including storage means for dividing N-term input data Y into a first set of even-term data Y (2i) and a second set of odd-term data Y (2i+1) and storing each of said first and second sets of data, wherein said i is an integer of 0.ltoreq.1.ltoreq.N/2-1, first reading means for reading in parallel one-bit data in the same order of said first set of all even-term data Y (2i), second reading means for reading in parallel one-bit data in the same order of said second set of all odd-term data Y (2i+1), and a ROM, storing in advance data indicating product sums of a corresponding coefficient and parallel bit data in a table form, for receiving parallel bit data as an address signal to output a corresponding partial sum, a method of carrying out one-dimensional inverse discrete cosine transform of N points, wherein N is 2.sup.m with m being a natural number, comprising the steps of:

• receiving N-term input data Y to generate said first set of even-term data Y (2i) and said second set of odd-term input data Y (2i+1);
• accessing said ROM using said first set of even-term data Y (2i) as an address signal and outputting a corresponding partial sum as a first set of intermediate data M (i);
• accessing said ROM using said second set of odd-term data Y (2i+1)) as an address signal and outputting a corresponding partial sum as a second set of intermediate data N (i);
• carrying out addition and subtraction of said first set of intermediate data M (i) and said second set of intermediate data N (i) to generate a first set of addition data and a second set of subtraction data;
• and
• outputting said first set of addition data and said second set of subtraction data in a predetermined order.

A processor having at least a function of carrying out one-dimensional discrete cosine transform of N-term input data X, wherein said N is a positive integer, said processor comprising:

• preprocessing means for carrying out addition and substraction for each of sets of predetermined two terms of said input data X to generate a first set of addition data and a second set of subtraction data;
• and
• matrix product means for obtaining a first matrix product of said first set of data from said preprocessing means and a predetermined first coefficient matrix, and a second matrix product of said second set of data and a predetermined second coefficient matrix, to produce an N term output Y;
• said matrix product means including
• storage means for sequentially receiving said second set of data from said preprocessing means to store the received data, each of said second set of data having a plurality of bits,
• parallel reading means for reading, in parallel and in order, one-bit data in the same bit figure of all of said second set of data stored in said storage means, and
• means responsive to said parallel reading means for producing said second matrix product.

A processor having at least a function of carrying out one-dimensional inverse discrete cosine transform of N-term multibit input data Y, wherein said N is a positive integer, said processor comprising:

• matrix product means for dividing said N-term multibit input data Y into a first set of multibit input data and a second set of input data and carrying out a product operation of said first set of input data and a first coefficient matrix and a product operation of said second set of input data and a second coefficient matrix, to generate a first set of intermediate data Mi and a second set of intermediate data Ni, wherein said i is an integer of 0.ltoreq.i.ltoreq.N/2-1;
• and
• postprocessing means for carrying out addition and substraction of two intermediate data in a predetermined relationship in said first set of intermediate data and said second set of intermediate data from said matrix product means to generate first and second sets of output data Xi;
• said matrix product means including
• storage means for sequentially receiving and storing said first set of multibit input data,
• first parallel reading means for reading, in parallel and in order, one-bit data in the same bit figure of all of said first set of data stored in said storage means, and
• means responsive to said first parallel reading means for producing said first set of intermediate data.