US 5,247,648 AGranted

Maintaining data coherency between a central cache, an I/O cache and a memory

AssigneeSun Microsystems, Inc.

InventorsJohn Watkins, David Labuda, William C. Van Loo

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Abstract

An I/O write back cache memory and a data coherency method is provided to a computer system having a cache and a main memory. The data coherency method includes partitioning the main memory into memory segments, dynamically assigning and reassigning the ownership of the memory segments either to the cache memory or the I/O write back cache memory. The ownership of the memory segments controls the accessibility and cacheability of the memory segments for read and write cycles performed by the CPU and I/O devices. During reassignment, various data management actions are taken to ensure data coherency. As a result, the I/O devices can perform read and write cycles addressed against the cache and main memory in a manner that increases system performance with minimal increase in hardware and complexity cost.

Claims16

Dependent claims

In a computer system comprising a central processing unit (CPU), a central cache, an input/output (I/O) cache, a memory, and a plurality of I/O devices, a method for maintaining data coherency between said central cache, said I/O cache, and said memory, said method comprising the steps of:

a) partitioning said memory into a plurality of memory segments;
b) assigning ownership for each of said memory segments to said central cache, each of said memory segments assigned to said central cache being eligible to be cached by said central cache only, but accessible by both read and write cycles of said CPU and of said I/O devices addressed to said memory;
c) classifying each of said I/O devices to one of a plurality of I/O device classes based on their logical I/O buffer and memory access characteristics;
d) allocating and deallocating said memory segments to said logical I/O buffers of said I/O devices, conditionally reassigning ownership of said memory segments being allocated and deallocated to said I/O cache and back to said central cache before said allocation and after said deallocation respectively, based on said I/O devices' classified I/O device classes, said memory segments assigned to said I/O cache being eligible to be cached by said central and I/O caches, but accessible by said read and write cycles of said I/O devices only;
e) detecting read and write cycles of said CPU and said I/O devices;
f) returning data to be read for said detected read cycles of said CPU from selected ones of (i) said central cache and (ii) said memory, and of said I/O devices from selected ones of (i) said I/O cache, (ii) said central cache, and (iii) said memory, respectively;
and
g) storing data to be written for write cycles of said CPU into selected ones of (i) said central cache, (ii) said memory, and (iii) both said central cache and memory, and of said I/O devices into selected ones of (i) said I/O cache and (ii) memory respectively.

5 more elements

A computer system comprising:

a) a memory comprising a plurality of memory segments;
b) a central cache coupled to said memory, a CPU, and a plurality of I/O devices, said central cache being assigned ownership of said memory segments, said central cache assigned memory segments being eligible to be cached by said central cache only, but accessible to read and write cycles of said CPU and said I/O devices addressed to said memory;
c) an I/O cache coupled to said memory and said I/O devices, said I/O cache being conditionally reassigned ownership of said memory segments based on classified I/O device classes of said I/O devices when said memory segments are allocated to logical I/O buffers of said I/O devices, said I/O cache assigned memory segments being eligible to be cached by said central cache and said I/O cache, but accessible to read and write cycles of said I/O devices addressed to said memory only;
d) an operating system allocating and deallocating said memory segments to said logical I/O buffers of said I/O devices, and conditionally reassigning ownership of said memory segments being allocated and deallocated to said I/O cache and back to said central cache before said allocation and after said deallocation respectively, based on said classified I/O device classes of said I/O devices;
e) said central processing unit (CPU) performing said read and write cycles addressed to said memory on behalf of process being executed by said CPU, data to be read for said read cycles of said CPU being returned from selected ones of (i) said central cache, and (ii) said memory, data to be written for said write cycles of said CPU being stored into selected ones of (i) said central cache, (ii) said memory, and (iii) both said central cache and memory;
and
f) said plurality of input/output (I/O) devices performing said read and write cycles addressed to said memory, said I/O devices being classified into said I/O device classes based on their logical I/O buffer and memory access characteristics, data to be read for said cycles of said I/O devices being returned from selected ones of (i) said I/O cache, (ii) said central cache, and (iii) said memory, data to be written for said write cycles of said I/O devices being stored into selected ones of (i) said I/O cache, and (iii) said memory.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/879,162Filed 30 Apr 1992 · continuation
Priority: 12 Apr 1990
Granted: 21 Sep 1993
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 12/0835
Using a bus scheme, e.g. with bus monitoring or watching means: for main memory peripheral accesses
G06F 12/0866
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: for…
G06F 12/0897
Caches characterised by their organisation or structure: with two or more cache hierarchy levels
G06F 12/0815
Multiuser, multiprocessor or multiprocessing cache systems: cache consistency protocols