Method for generating a checksum

A method for generating a checksum byte of q electrical bit signals from a sequence of q-bit-signal bytes which collectively form a bit signal string, comprising the computer-implemented steps of:

• segmenting said bit signal string into three or more bit signal groups each including two or more bytes,
• storing an electrical representation of a weighted sum of the bytes of a first bit signal group in a first register, wherein each byte of said first bit signal group is multiplied by a factor derived from the position of said byte in said first bit signal group,
• storing an electrical representation of an unweighted sum of the bytes of said first bit signal group in a second register,
• storing an electrical representation of a zero value in a third register,
• updating the value stored in said first register by adding the value stored in said first register to an electrical representation of a weighted sum of the bytes of a second bit signal group, wherein, before summing, each byte of said second bit signal group is multiplied by a factor derived from the position of said byte in said second bit signal group, and storing an electrical representation of the result in said first register,
• updating the value stored in said third register by adding the value stored in said third register to the value stored in said second register, and storing an electrical representation of the result in said third register, then
• updating the value stored in said second register by adding the value stored in said second register to an electrical representation of the unweighted sum of the byes of said second bit signal group, and storing an electrical representation of the result in said second register;
• repeating said updating steps for a third and further bit signal group until all bit signal groups have been used, and then
• generating said checksum byte by multiplying the value stored in said third register by the number of bytes in said bit signal groups, and adding the product to the value stored in said first register.

A method for generating a checksum byte of q electrical bit signals from a sequence of q-bit-signal bytes which collectively form a bit signal string, comprising the computer-implemented steps of:

• segmenting said bit signal string into three or more bit signal groups each including two or more bytes,
• storing the bytes of a first bit signal group in a first register,
• storing an electrical representation of a zero value in a second register,
• updating the value stored in said second register by adding the unweighted sum of the bytes stored in said first register to the value stored in said second register and storing an electrical representation of the result in said second register, then
• updating the value stored in said first register by adding each respective byte stored in said first register to a corresponding byte of a second bit signal group, and storing the result in said first register in place of said respective byte from said first register,
• repeating said updating steps for a third and further bit signal groups until all bit signal groups have been used,
• generating a weighted sum of the bytes stored in said first register, wherein, before summing, each byte stored in said first register is multiplied by a factor derived from the position of said byte in said register,
• generating a product of the value stored in said second register and the number of bytes in said bit signal groups, and
• generating said checksum byte by adding said weighted sum to said product.

The method for generating a weighted sum of a sequence of electrical input bit signals arranged into q-bit-signal bytes and collectively forming an input bit group, comprising the computer-implemented steps of:

• producing a mask bit group of mask bit signals, said mask bit group including alternating positive and negative collections of q-bit-signal bytes, wherein every mask bit signal in every byte of a positive collection has a positive logical value, and every mask bit signal in every byte of a negative collection has a negative value,
• forming an intermediate bit group of intermediate bit signals, each intermediate bit signal representing the logical AND of an input bit signal holding a given position within said input bit group and a mask bit signal holding said given position within said mask bit group, said intermediate bit signal holding a position other than said given position within said intermediate bit group,
• repeating said producing and forming steps to form additional intermediate bit groups not all of which are identical, and
• generating said weighted sum by adding said intermediate bit groups.

Apparatus for generating a checksum byte of q electrical bit signals from a sequence of q-bit-signal bytes which collectively form a bit signal string, comprising:

• means for segmenting said bit signal string into two or more bit signal groups each including two or more bytes,
• means for computing a first weighted sum of the bytes of a first and a second bit signal group, wherein, before summing, each byte of said first bit signal group is multiplied by a factor derived from the position of said byte in said first bit signal group, and each byte of said second bit signal group is multiplied by a factor derived from the position of said byte in said second bit signal group,
• means for computing a second unweighted sum of the bytes of said first bit signal group, and then
• means for computing said checksum byte by multiplying said second sum by the number of bytes in said bit signal groups, and adding the product to said first sum.

Apparatus for generating a checksum byte of q electrical bit signals from a sequence of q-bit-signal bytes which collectively form a bit signal string, comprising:

• means for segmenting said bit signal string into three or more bit signal groups each including two or more bytes;
• means for storing an electrical representation of a weighted sum of the bytes of a first bit signal group in a first register, wherein each byte of said first bit signal group is multiplied by a factor derived from the position of said byte in said first bit signal group;
• means for storing an electrical representation of an unweighted sum of the bytes of said first bit signal group in a second register;
• means for storing an electrical representation of a zero value in a third register;
• means for
• updating the value stored in said first register by adding the value stored in said first register to an electrical representation of a weighted sum of the bytes of a second bit signal group, wherein, before summing, each byte of said second bit signal group is multiplied by a factor derived from the position of said byte in said second bit signal group, and storing and electrical representation of the result in said first register,
• updating the value stored in said third register by adding the value stored in said third register to the value stored in said second register, and storing an electrical representation of the result in said third register, and
• updating the value stored in said second register by adding the value stored in said second register to an electrical representation of the unweighted sum of the bytes of said second bit signal group, and storing an electrical representation of the result in said second register, and
• repeating said updating steps for a third and further bit signal group until all bit signal groups have been used;
• and
• means for generating said checksum byte by multiplying the value stored in said third register by the number of byte in said bit signal groups, and adding the product to the value stored in said first register.

Apparatus for generating a checksum byte of q electrical bit signals form a sequence of q-bit-signal bytes which collectively form a bit signal string, comprising:

• means for segmenting said bit signal string into three or more bit signal groups each including two or more bytes,
• means for storing the bytes of a first bit signal group in a first register,
• means for storing an electrical representation of a zero value in a second register,
• means for
• updating the value stored in said second register by adding the unweighted sum of the bytes stored in said first register to the value stored in said second register and storing an electrical representation of the result in said second register, then
• updating the value stored in said first register by adding each respective byte stored in said first register to a corresponding byte of a second bit signal group, and storing the result in said first register in place of said respective byte from said first register, and
• repeating said updating steps for a third and further bit signal groups unit all bit signal groups have been used,
• means for generating a weighted sum of the bytes stored in said first register, wherein, before summing, each byte stored in said first register is multiplied by a factor derived from the position of said byte in said register,
• means for generating a product of the value stored in said second register and the number of bytes in said bit signal groups, and
• means for generating said checksum byte by adding said weighted sum to said product.

Apparatus for generating a weighted sum of a sequence of electrical input bit signals arranged into q-bit-signal bytes and collectively forming an input bit group, comprising:

• means for producing a mask bit group of mask bit signals, said mask bit group including alternating positive and negative collections of q-bit-signal bytes, wherein every mask bit signal in every byte of a positive collection has a positive logical value, and every mask bit signal in every byte of a negative collection has a negative value,
• means for forming an intermediate bit group of intermediate bit signals, each intermediate bit signal representing the logical AND of an input bit signal holding a given position within said input bit group and a mask bit signal holding said given position within said mask bit group, said intermediate bit signal holding a position other than said given position within said intermediate bit group,
• wherein said producing and forming means generates multiple intermediate bit groups not all of which are identical, and further comprising
• means for generating said weighted sum by adding said intermediate bit groups.