Method for manufacture of multilayer circuit board

A method for the formation of a circuit board having two or more layers of circuitry, said method comprising the steps of applying a dielectric coating over a first circuit layer, said coating having imaged openings defining interconnections, catalyzing the surface of said permanent dielectric coating and the imaged openings by contact with an electroless plating catalyst, applying a sacrificial coating over said catalyzed permanent dielectric coating, said sacrificial coating having imaged openings in a negative pattern of a desired circuit pattern, removing electrolessly plating catalyst from the surface of said permanent dielectric coating where not coated by said sacrifical coating to provide a catalyst free surface, removing the remainder of the sacrificial coating, and electrolessly plating metal into said openings for interconnections and onto catalyzed surfaces of said permanent dielectric coating, whereby, when plated, there is formed a second circuit in electrical contact with the first circuit.

A method for the formation of a circuit board having two or more layers of circuitry, said method comprising the steps of applying a first permanent dielectric coating over a first circuit layer, said coating having imaged openings defining interconnections, applying a sacrificial coating over said first permanent dielectric coating, said sacrificial coating having imaged openings defining a circuit pattern, catalyzing the surfaces of said first permanent dielectric coating where bared including the recesses defined by said permanent dielectric coating and the surfaces of said sacrifical coating with an electroless plating catalyst, removing said sacrificial coating together with plating catalyst thereon and applying a second permanent dielectric coating over the first permanent dielectric coating, said second permanent dielectric coating having imaged openings corresponding to those contained in the sacrificial coating thereby providing recesses defining interconnections and circuit lines, and electrolessly plating metal into said openings for interconnections and circuits, whereby, when plated, there is formed a second circuit in electrical contact with said first circuit free of plating catalyst between layers of permanent dielectric coating.

A method for the formation of a circuit board having two or more layers of circuitry, said method comprising the steps of applying a first permanent dielectric coating over a first circuit layer, said coating having imaged openings defining interconnections, applying a sacrificial coating over said first permanent dielectric coating, said sacrificial coating having imaged openings defining a circuit pattern, catalyzing the surfaces of said permanent dielectric coating where bared including the recessed defined by said permanent dielectric coating and the surfaces of said sacrificial coating with an electroless plating catalyst, removing said sacrificial coating toether with plating catalyst thereon, electroless metal plating into said openings for interconnections and onto catalyzed surfaces of said dielectric coating, whereby, when plated, there is formed a second circuit in electrical contact with said first circuit, and filling spaces between circuit lines plated onto the permanent dielectric coating with an additional layer of a permanent dielectric coating whereby the interface between dielectric coatings is free of catalytic material.

A method for the formation of a circuit board having two or more layers of circuitry, said method comprising the steps of applying a permanent dielectric coating over a first circuit layer, said coating having imaged openings defining interconnections, activating bared metal on said first circuit layer to render the same electrolessly plateable without application of an electroless metal plating catalyst, filling said openings defining interconnections with metal by electrolessly plating metal into said openings, subsequently forming a separate circuit over said permanent dielectric coating having metallized interconnections, whereby there is formed a second circuit in electrical contact with said first circuit.

A method for the formation of a circuit board having two or more layers of circuitry, said method comprising the steps of applying a first permanent dielectric coating over a first circuit layer, said coating having imaged openings defining interconnections, applying a sacrificial coating having imaged openings in a negative pattern of said image in the first permanent dielectric coating, contacting bared portions of said first permanent dielectric coating with an electroless plating catalyst poison whereby catalyst poison contacts all surfaces of the sacrificial coating and underlying first dielectric coating exposed within the imaged openings of the sacrifical coating, removing said sacrificial coating together with catalyst poison thereon, contacting all exposed surfaces with an electroless plating catalyst whereby non-poisoned surfaces of said first permanent dielectric coating and the exposed underlying substrate are catalyzed with the electroless plating catalyst, applying a second permanent dielectric coating over the first permanent dielectric coating, said second permanent dielectric coating having imaged openings defining a conductor pattern and interconnections, and electrolessly plating metal into said openings for interconnections and circuitry.

A method for the formation of a circuit board having two or more layers of circuitry, said method comprising the steps of applying a dielectric coating over a first circuit layer, said coating having imaged openings defining interconnections, applying a sacrificial coating having imaged openings in a negative pattern of a desired circuit pattern, contacting bared portions of said permanent dielectric coating and the surfaces of the sacrificial coating with an electroless plating catalyst poison, removing the remainder of the sacrificial coating together with the catalytic poison over its surface, contacting all exposed surfaces with an electroless plating catalyst whereby non-poisoned surfaces of said permanent dielectric coating and the exposed underlying substrate are catalyzed with the electroless plating catalyst, and electroless plating metal into said openings for interconnections and onto catalyzed surfaces of said permanent dielectric coating, whereby, when plated, there is formed a second circuit in electrical contact with said first circuit.

A method for the formation of a printed circuit board having two or more layers of circuitry, said method comprising the steps of applying a first dielectric coating over a first circuit, said first dielectric coating being filled with particles of an electroless plating precursor and having imaged openings defining interconnections, applying a second permanent dielectric coating over the first permanent dielectric coating, said second permanent dielectric coating having imaged openings defining a conductor pattern and interconnections, baring and activating the particles of electroless plating catalyst precursor on the surfaces of said first permanent dielectric coating whereby only the surfaces of said first permanent dielectric are rendered catalytic to electroless metal deposition, and electrolessly plating metal into said openings for interconnections defined by said first permanent dielectric coating and circuitry defined by said first and second permanent dielectric coatings, whereby, when plated, there is formed a second circuit in electrical contact with said first circuit.

A method for the formation of a printed circuit board having two or more layers of circuitry, said method comprising the steps of applying a first dielectric coating over a first circuit, said dielectric coating being filled with particles of an electroless plating precursor and having imaged openings defining interconnections, applying a sacrificial coating over said first dielectric coating having imaged openings corresponding to the imaged openings in said first dielectric coating, baring and activating the particles of the electroless plating catalyst precursor on the surfaces of said first permanent dielectric coating whereby the bared surfaces of said first permanent dielectric including the recesses therein are rendered catalytic to electroless metal deposition, removing said sacrificial coating, electrolessly plating metal into said openings for interconnections to the full thickness of the openings in the dielectric coating and applying a second circuit layer over the first permanent dielectric coating having said metallized interconnections, whereby, there is formed a second circuit in electrical contact with said first circuit.

A method for the formation of a printed circuit board having two or more layers of circuitry, said method comprising the steps of applying a dielectric coating over a first circuit, said permanent dielectric coating being filled with particles of an electroless plating catalyst precursor, laser ablating recesses defining a circuit pattern in said dielectric coating to a thickness less than the full thickness of the dielectric coating and laser ablating recesses defining interconnections through the full thickness of said dielectric coating, baring and activating the particles of the electroless plating catalyst precursor on the surfaces of said dielectric coating, and electrolessly plating metal into said openings for interconnections and circuitry, whereby, when plated, there is formed a second circuit in electrical contact with said first circuit.

A method for the formation of a printed circuit board having two or more layers of circuitry, said method comprising the steps of applying a permanent, light sensitive positive working dielectric coating over a first circuit layer, surface imaging the dielectric coating through a master defining a desired circuit pattern and developing said surface imaged dielectric coating to form recesses to a thickness less than the full thickness of the dielectric coating defining a desired circuit pattern, imaging said dielectric coating a second time through a mask defining a desired pattern of interconnections and developing said dielectric coating through the entire thickness of the dielectric coating to form recesses defining said interconnections, selectively catalyzing recesses defining interconnections and circuit lines and electrolessly plating metal into all said recesses whereby, when plated, there is formed a second circuit in electrical communication with said first circuit.