Floating gate nonvolatile memory with reading while writing capability

A floating gate nonvolatile memory circuitry residing on a single silicon substrate, comprising:

• a first memory array;
• a first address register for storing a first address for the first memory array;
• a second memory array;
• a second address register for storing a second address for the second memory array;
• a multiplexer coupled to the first memory array and the second memory array at a first end and an output of the memory circuitry at a second end for selectively coupling one of the first memory array and the second memory array to the output at a time;
• array select circuitry responsive to (1) incoming array select information associated with the first address and (2) memory operation control information for selecting the first memory array for a reprogramming operation and for allowing a read operation with respect to the second memory array during the reprogramming operation of the first memory array, wherein the array select circuitry directs the first address to the first address register for the reprogramming operation in response to the incoming array select information and the memory operation control information received and directs the second address to the second address register for the read operation during the reprogramming operation of the first memory array, wherein the array select circuitry prevents the second address from entering the first address register during the reprogramming operation of the first memory array, wherein the array select circuitry controls the multiplexer for coupling the second memory array to the output during the reprogramming operation of the first memory array and the read operation of the second memory array such that the second memory array can undergo the read operation when the first memory array is undergoing the reprogramming operation.