Timebase corrector with drop-out compensation
AssigneeSony Corporation
InventorHajime Nishimura
Life of this patent
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Abstract
A timebase corrector is provided, in which an input video signal is written in a timebase error correcting memory on the basis of a clock pulse synchronized with a synchronizing signal in the input video signal and the signal written in the time base error correcting memory is read out on the basis of a read clock pulse synchronized with a reference signal to thereby correct a timebase error. In this timebase corrector, when a drop-out of a first vertical synchronizing signal in the input video signal occurs, the write of the input video signal in the timebase error correcting memory is inhibited, and a timebase error is corrected by the input video signal already written in the memory until a second vertical synchronizing signal is detected.
Claims3
A timebase corrector in which an input video signal is written in a timebase error correcting memory on the basis of a clock pulse synchronized with a synchronizing signal of said input video signal and a signal written in said timebase error correcting memory is ready out on the basis of a read clock pulse synchronized with a reference synchronizing signal to thereby correct a time base of the input video signal, comprising:
- a) write means for writing a video signal;
- b) a memory in which said video signal is written by said write means;
- c) means for reading a timebase corrected video signal from said memory;
- d) first synchronizing separating means for extracting a first synchronizing signal from said video signal;
- e) second synchronizing separating means for extracting a second synchronizing signal from said video signal;
- f) write-enable signal generating means for generating a write-enable signal on the basis of said first synchronizing signal to place said memory in a writable state;
- g) drop-out detecting means for detecting a drop-out of said second synchronizing signal;
- and
- h) means connected to the write-enable signal generating means for generating a control signal to the write-enable signal generating means by which a writing in said memory by the write means is disabled for as long as said drop-out detecting means detects a drop-out of said second synchronizing signal.
A timebase corrector in which an input video signal is written in a timebase error correcting memory on the basis of a clock pulse synchronized with a synchronizing signal of said input video signal and a signal written in said timebase error correcting memory is read out on the basis of a read clock pulse synchronized with a reference synchronizing signal to thereby correct a time base of the input video signal, comprising:
- a) write means for writing a video signal;
- b) a memory in which said video signal is written;
- p1 c) means for reading a timebase corrected video signal from said memory;
- d) first synchronizing separating means for extracting a second synchronizing signal from said video signal;
- e) second synchronizing separating means for extracting a second synchronizing signal from said video signal;
- f) write-enable signal generating means for generating a write-enable signal on the basis of said first synchronizing signal to place said memory in a writable state, wherein said write-enable signal generating means is comprised of a counter for counting the number of said first synchronizing signal and a read only memory (ROM) for generating a predetermined pattern signal in response to an output of said counter;
- g) drop-out detecting means for detecting a drop-out of said second synchronizing signal;
- and
- h) means for generating a signal by which a writing in said memory is disabled when said drop-out detecting means detects a drop-out of said second synchronizing signal.
Dependencies are inferred from the claim text.