Versatile programmable logic cell for use in configurable logic arrays

A programmable logic circuit comprising:

• first, second and third logic gates, each having at least first and second inputs and at least a first output, said first and second inputs to the third logic gate being connected to the first outputs of the first and second logic gates, respectively;
• a configurable-interconnect element having a first input and first and second outputs, said first output being connected to the first input of the first logic gate and said second output being connected to the first input of the second logic gate;
• and
• a register having a data input and a data output, the data input being connected to the first output of the third logic gate.

A programmable logic cell for use in a programmable logic cell array, said cell comprising:

• first, second, and third cell inputs;
• at least a first cell output;
• first, second and third logic gates, each having at least first and second inputs and at least a first output, said first and second inputs to the third logic gate being connected to the first outputs of the first and second logic gates, respectively;
• a configurable-interconnect element having a first input and first and second outputs, said first output being connected to the first input of the first logic gate and said second output being connected to the first input of the second logic gate;
• means for connecting the first cell input to the first input of the first logic gate;
• means for connecting the second cell input to the first input of the second logic gate;
• means for connecting the third cell input to the first input of the configurable-interconnect element;
• and
• means for connecting the output of the third logic gate to the first cell output.

In a programmable logic array, said array including a means for supplying K configuration control signals and their logical inverses, a programmable default-output multiplexer responsive to the configuration control signals for connecting one of K input terminals or a default value to an output terminal, said multiplexer comprising:

• K pass gates, wherein each pass gate can connect one of the K input terminals to the output terminal when activated by the value of one of the K configuration control signals and its logical inverse, each pass gate comprising an N-type MOS transistor including drain, source, and gate terminals, wherein the drain terminal connects to one of the K input terminals, the source terminal connects to the output terminal, and the gate terminal connects to one of the K configuration control signals, and a P-type MOS transistor including drain, source, and gate terminals, wherein the source terminal connects to one of the K input terminals, the drain terminal connects to the output terminal, and the gate terminal connects to the logical inverse of the configuration control signal;
• and
• a chain of K MOS transistors for supplying a default value to the output terminal when none of the K pass gates is activated, each of the K MOS transistors in the chain including drain, source and gate terminals, wherein the chain is formed by connecting the source terminal of each MOS transistor in the chain to the drain terminal of the next MOS transistor in the chain, one of the source/drain terminals at an end of the chain connects to a means for supplying a default value and the source/drain terminal at the other end of the chain connects to the output terminal of the multiplexer, and the gate voltage of each MOS transistor in the chain is determined by a different one of the K configuration control signals which control the K pass gates whereby all MOS transistors in the chain are conducting only when all the K pass gates are not activated.

A programmable logic cell for use in a programmable logic array, said logic cell comprising:

• means for supplying a configuration control;
• first, second and third cell inputs;
• a cell output;
• first and second logic gates each having first and second inputs;
• a third logic gate having at least two inputs;
• means for connecting said first cell input to said first input of said first logic gate;
• means for connecting said second cell input to said first input of said second logic gate;
• means responsive to the configuration control for connecting either said third cell input or a constant logical value to said second input of said first logic gate;
• means responsive to the configuration control for connecting either an inverted form of said third cell input or a constant logical value to said second input of said second logic gate;
• means for connecting the output of said first logic gate to an input of said third logic gate;
• means for connecting the output of said second logic gate to an input of said third logic gate;
• and
• means for connecting the output of said third logic gate to the cell output.

A programmable logic array comprising:

• a plurality of logic cells, wherein each cell except those at the edges of the array has four nearest-neighbor cells, one to the left (or West), one to the right (or East), one above (or to the North), and one below (or to the South) so as to form an array in which said logic cells are aligned in rows and columns, each cell comprising:
• means for supplying a configuration control;
• four "A" inputs, one received from each of the nearest-neighbor cells;
• four "B" inputs, one received from each of the four nearest-neighbor cells;
• first, second and third logic gates, each having at least first and second inputs and at least a first output, said first and second inputs to the third logic gate being connected to the outputs of the first and second logic gates, respectively;
• a configurable-interconnect element having a first input and first and second outputs, said first output being connected to the first input of the first logic gate and said second output being connected to the first input of the second logic gate;
• means programmably responsive to the configuration control means for connecting one of the "A" inputs to the second input of the first logic gate;
• means programmably responsive to the configuration control means for connecting one of the "B" inputs to the second input of the second logic gate;
• and
• means responsive to the configuration control means for connecting the output of the third logic gate to the "A" inputs and/or the "B" inputs of the four nearest-neighbor cells.

A programmable logic array comprising:

• a plurality of logic cells, wherein each cell except those at the edges of the array has four nearest-neighbor cells, one to the left (or West), one to the right (or East), one above (or to the North), and one below (or to the South) so as to form an array in which said logic cells are aligned in rows and columns, each cell comprising:
• means for supplying a configuration control;
• four inputs, one received from each of the nearest-neighbor cells;
• first, second and third logic gates, each having at least first and second inputs and at least a first output, said first and second inputs to the third logic gate being connected to the first outputs of the first and second logic gates, respectively;
• a configurable-interconnect element having a first input and first and second outputs, said first output being connected to the first input of the first logic gate and said second output being connected to the first input of the second logic gate;
• means programmably responsive to the configuration control means for connecting one of the four nearest-neighbor inputs to the second input to the first logic gate;
• means programmably responsive to the configuration control means for connecting one of the four nearest-neighbor inputs to the second input to the second logic gate;
• North output-selecting means for connecting one of a plurality of candidate North outputs, including the inputs from the South, East, and West nearest-neighbor cells and the output of the third logic gate, to an input of the nearest-neighbor cell to the North;
• South output-selecting means for connecting one of a plurality of candidate South outputs, including the inputs from the North, East, and West nearest-neighbor cells and the output of the third logic gate, to an input of the nearest-neighbor cell to the South;
• East output-selecting means for connecting one of a plurality of candidate East outputs, including the inputs from the North, South and West nearest-neighbor cells and the output of the third logic gate, to an input of the nearest-neighbor cell to the East;
• and,
• West output-selecting means for connecting one of a plurality of candidate West outputs, including the inputs from the North, South, and East nearest-neighbor cells and the output of the third logic gate, to an input of the nearest-neighbor cell to the West.