Method and apparatus for fault tolerance

A computer system comprising:

• a first computer comprising:
• a first memory,
• a first central processing unit in communication with the memory,
• a first input port in communication with the memory and the first central processing unit,
• a first algorithm disposed in the first memory, said first algorithm produces a first output and produces a certification trail based on input received by the input port when the first algorithm is executed by the first central processor;
• a second computer comprising a second memory,
• a second central processing unit in communication with the second memory and the first central processing unit;
• a second input port in communication with the second memory and the second central processing unit;
• a second algorithm disposed in the second memory, said second algorithm produces a second output based on the input and the certification trail when the second algorithm is executed by the second central processing unit, said second algorithm having a faster execution time than the first algorithm for a given input;
• and
• a mechanism for comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same.

A method for achieving fault tolerance in a central processing unit comprising the steps of:

• executing a first algorithm in the central processing unit on input so that a first output and a certification trail are produced;
• executing a second algorithm in the central processing unit on the input and on the certification trail so that a second output is produced, said second algorithm having a faster execution time than the first algorithm for a given input;
• and
• comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same.

A computer comprising:

• a memory,
• a central processing unit in communication with the memory,
• a first input port in communication with the memory and the central processing unit,
• a first algorithm disposed in the memory, said first algorithm produces a first output and a certification trail based on input received by the input port when the input is executed by the central processing unit;
• a second algorithm disposed in the memory, said second algorithm produces a second output based on the input and on at least a portion of the certification trail when the second algorithm is executed by the central processing unit, said second algorithm having a faster execution time than the first algorithm for a given input;
• and
• a mechanism for comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same.