Integrated thin film transistor electrographic writing head

A method for operating an electrographic writing head for writing image data onto a medium said electrographic writing multiple lines of writing head having a plurality of four-phased dynamic shift registers, each of said dynamic shift registers connected to buffers, said buffers one of a plurality of connected to a plurality of memory cells, each of said memory cells connected to one of a plurality of latches, said latches are connected to high voltage driver cells, said high voltage driver cells are connected to writing electrodes, said writing electrodes writes data onto a medium, including the steps of:

• a) pulsing a write line for each latch on said writing head for effectively disconnecting said high voltage cascode circuit from said memory cell;
• b) pulsing a preset input of each of said memory cells on said writing head for setting an output of each of said memory cell;
• c) shifting a pulse serially through said four-phased dynamic shift registers and said buffers enabling loading of data from a portion of a scanline of data into a group of memory cells in turn, until each of said group of memory cells on said writing head has been written to;
• d) pulsing said write line of each of said latches on said writing head simultaneously causing said data from said memory cells to be latched into said latches and simultaneously presenting said scanline of data to said writing electrodes through said high voltage driving cells, said writing electrodes writing said scanline of data simultaneously onto said medium;
• and
• e) repeating steps a-d until of all of said multiple lines of image data is written onto said medium.

A method for operating an electrographic writing head for writing multiple lines of image data onto a medium in a writing direction, said electrographic writing head having a plurality of sections, said sections are aligned in a linear array wherein one or more of said sections are offset from others of said sections, each of said sections having a plurality of dynamic four-phased dynamic shift registers, each of said four-phased dynamic shift registers is connected to one of a plurality of buffers, each of said one of a plurality of buffers is connected to a plurality of memory cells, each of said memory cells is connected to one of a plurality of latches, each one of said latches if connected to one of a plurality of high voltage driver circuits, each of said high voltage driver circuits is connected to one of plurality of writing electrodes, each of said writing electrodes writes data onto said medium, including the steps of:

• a) pulsing a write line for each of a plurality of latches on said writing head low effectively disconnecting said high voltage driver circuits from said memory cells;
• b) pulsing a preset input of each of said memory cells on said writing head high setting an output of each of said memory cells low;
• c) shifting a low pulse serially through each of said four-phased dynamic shift registers and each of said buffers for each section enabling loading of a portion of an entire scanline of data into said memory cells;
• d) pulsing said write line of each of said sections separately from pulsing said write line on others of said sections to be written onto said medium a section at a time, effectively eliminating the offset between said sections when writing said entire scanline of data;
• and
• e) repeating steps a-d until all of said multiple lines of image data is written onto said medium.