Lightly doped drain MOSFET with reduced on-resistance
AssigneeSiliconix Incorporated
InventorsRichard K. Williams, Randolph D. Mah
Life of this patent
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Abstract
Construction method and apparatus for lightly doped drain MOSFET that has low or minimum drift on-state resistance and maintains high voltage blocking in the off-state. Temperature sensitivity of the electrical properties of the MOSFET are also reduced relative to MOSFETs produced by processes such as SIPOS. Voltage level shifting of p-channel and n-channel MOSFETs, produced according to the invention, relative to another voltage level is easily accomplished.
Claims22
MOSFET apparatus having reduced on-resistance and improved current characteristics, the apparatus comprising:
- a substrate region of first electrical conductivity type that has a top surface;
- source and drain regions, each more heavily doped than said substrate region, of second electrical conductivity type, spaced apart from each other and each forming a part of said top surface of said substrate region;
- a body region of second conductivity type material doped at a level intermediate that of said substrate region and said source region, surrounding said source region and forming a part of said top surface of said substrate region, so that said source region becomes an island in said body region;
- an oxide region having a top surface, being adjacent to said top surface of said substrate region, and including a semiconductor oxide material, overlying at least a portion of said source and drain regions and overlying substantially all of said substrate region that lies between said source and drain regions;
- a drift region positioned between said source and drain regions and forming a part of said top surface of said substrate region, spaced apart from at least one of said source region and said drain region and defining a gap therebetween, and forming a part of said top surface of said substrate region, said drift region being of second conductivity type;
- a gate overlying at least a portion of said gap and being positioned within the interior of said oxide region and overlying a portion of said substrate region that lies between said source and drain regions;
- means electrically connected to said gate for impressing a voltage on said gate;
- a second oxide region of high quality oxide, positioned between said gate and a portion of said top surface of said substrate region;
- a first electrical contact contiguous to said source region, a second electrical contact contiguous to said drain region, and a third electrical contact contiguous to said gate;
- a drift electrode of electrically conducting material positioned adjacent to said top surface of said oxide region, overlying at least a portion of said drift region and at most only a portion of said gate and having a voltage impressed on said drift electrode, to enhance the conductivity of said drift region when the MOSFET is on and to suppress the conductivity when the MOSFET is in the off-state;
- and
- means electrically connected to said drift electrode for impressing a first voltage on the drift electrode when the MOSFET is on and to impress a second voltage that differs from the first voltage when the MOSFET is not on, the first voltage being more positive than the voltage impressed on said gate.
Apparatus for reducing the on-state resistance during voltage transition and improving the current characteristics of a p-channel MOSFET or an n-channel MOSFET, the apparatus comprising:
- a substrate region of a first electrical conductivity type that has a top surface;
- source and drain regions each more heavily doped than said substrate region, of second electrical conductivity type, spaced apart from each other and each forming a part of said top surface of said substrate;
- a body region of second conductivity type material doped at a level intermediate that of said substrate region and said source region, surrounding said source region and forming a part of said top surface of said substrate so that said source region becomes an island in said body region;
- an oxide region having a top surface, being adjacent to said top surface of said substrate, and including a semiconductor oxide material that overlies at least a portion of said source and drain regions and that overlies substantially all of said substrate region that lies between said source and drain regions;
- a drift region positioned between said source and drain regions and forming a part of said top surface of said substrate, spaced apart from at least one of said source region and said drain region and defining a gap therebetween, said drift region being of second electrical conductivity type;
- a gate overlying at least a portion of said gap and being positioned within the interior of said oxide region and overlying a portion of said substrate region that lies between said source and drain regions;
- means electrically connected to said gate for impressing a voltage on said gate;
- a second oxide region of high quality oxide, positioned between said gate and a portion of said top surface of said substrate;
- a first electrical contact contiguous to said source region, a second electrical contact contiguous to said drain region, and a third electrical contact contiguous to said gate;
- a drift electrode of electrically conducting material overlying at least a portion of said drift region and having a predetermined voltage impressed on said drift electrode, equal to the drain potential to enhance the conductivity of said drift region when the MOSFET is on during a voltage transition;
- and
- means electrically connected to said drift electrode for impressing a second voltage on said drift electrode when the MOSFET is on and to impress a third voltage that differs from said first voltage when the MOSFET is not on, the second voltage being more positive than the voltage impressed on said gate.
Apparatus for reducing the on-state resistance and improving the current characteristics of a MOSFET, the apparatus comprising:
- a well of material of a first electrical conductivity type that has a top surface and a bottom surface;
- a drain region more strongly doped than said well, of a second electrical conductivity type that is substantially opposite to the first conductivity type, with said drain region forming a part of said top surface of said well;
- first and second source regions, each more heavily doped than said drain region, of a second conductivity type and forming a part of said top surface of said well, with said two source regions being spaced apart from one another and each source region being spaced apart from said drain region, with said drain region being positioned between said first source region and said second source region;
- a first oxide region having a top surface, being adjacent to and above said top surface of said well, and including a semiconductor oxide material that overlies at least a portion of said drain region and said first source region and that overlies substantially all of said well that lies between said drain and first source regions;
- a second oxide region having a top surface, being adjacent to said top surface of said well, and including a semiconductor oxide material that overlies at least a portion of said drain region and said second source region and that overlies substantially all of said well that lies between said drain and second source regions;
- a first drift region positioned between said drain and first source regions and forming a part of said top surface of said well, spaced apart from at least one of said drain region and said first source region and defining a first gap therebetween, said first drift region being of second conductivity type;
- a second drift region positioned between said drain and second source regions and defining a part of said top surface of said well, spaced apart from at least one of said drain region and said second source region and forming a second gap therebetween, said second drift region being of second conductivity type;
- a first gate overlying at least a portion of said first gap and being positioned within the interior of said first oxide region and overlying a portion of said well that lies between said drain and first source regions;
- a second gate overlying at least a portion of said second gap and being positioned within the interior of said second oxide region and overlying a portion of said well that lies between said drain and second source regions;
- means electrically connected to both said gates for impressing a voltage on both said gates;
- a third oxide region of high quality oxide, positioned between said first gate and a portion of said top surface of said well;
- a fourth oxide region of high quality oxide, positioned between the second gate and a portion of said top surface of said well;
- a first drift electrode of electrically conducting material positioned adjacent to said top surface of said first oxide region, overlying at least a portion of said first drift region and at most only a portion of said first gate and having a voltage impressed on said first drift electrode which enhances the conductivity of said first drift region when the device is on and to suppress the conductivity when the device is in the off-state;
- a second drift electrode of electrically conducting material positioned adjacent to said top surface of said second oxide region, overlying at least a portion of said second drift region and at most a portion of said second gate and having a voltage impressed on said second drift electrode which enhances the conductivity of said second drift region when the device is on and suppresses the conductivity when the apparatus is off, where said first and second drift electrodes may be electrically connected to each other;
- a buried layer, including material of first conductivity type, positioned adjacent to the bottom surface of said well and underlying substantially all of said first and second source regions, first and second drift regions and drain region;
- a first body contact region, including material of first conductivity type, forming a part of said top surface of said well and being positioned contiguous to said first source region and to said well so that said first source region lies between said first body contact region and said drain region;
- a second body contact region, including material of first conductivity type, forming a part of said top surface of said well and being positioned contiguous to said second source region so that said second source region lies between said second body contact region and said drain region;
- and
- a first electrical contact contiguous to said first source region and to said first body contact region, a second electrical contact contiguous to said second source region and to said second body contact region, a third electrical contact contiguous to said first gate, a fourth electrical contact contiguous to said second gate, and a fifth electrical contact contiguous to said drain region.
Apparatus for reducing the on-state resistance of, and improving the current characteristics of, a MOSFET, apparatus comprising:
- a substrate region of first electrical conductivity type that has a top surface;
- source and drain regions of second conductivity type, more heavily doped than said substrate region, spaced apart from each other and each forming a part of said top surface of said substrate region;
- a drift region of second electrical conductivity type opposite to that of the first conductivity type, formed at said top surface of said substrate and of a predetermined thickness having an interface with said substrate region, and extending between said source region and said drain region;
- a buried layer of first conductivity type, doped at a level intermediate that of said substrate region and said source region, that is adjacent to a portion of the substrate region-drift region interface;
- a body region of first conductivity type in said substrate region top surface that surrounds said source region so that said source region becomes an island in said body region, with said body region being spaced apart laterally from said drain region and being spaced apart vertically from said buried layer;
- an oxide region having a top surface, being adjacent to the top surface of said drift region, and including a semiconductor oxide material, overlying at least a portion of said source and drain regions and overlying substantially all of said drift region that lies between said source and drain regions;
- a gate overlying at least a portion of said drift region and being positioned within the interior of said oxide region and overlying a portion of said drift region that lies between said source and drain regions;
- means electrically connected to said gate for impressing a voltage on said gate;
- a second oxide region of high quality oxide, positioned between said gate and a portion of said top surface of said substrate;
- and
- a drift electrode of electrically conducting material positioned adjacent to said top surface of said oxide region, overlying at least a portion of said drift region and at most only a portion of said gate and having a voltage impressed on said drift electrode, to enhance the conductivity of said drift region when the MOSFET is on and to suppress the conductivity when the MOSFET is in an off-state, the voltage impressed on said drift electrode being more positive than the voltage impressed on said gate when the MOSFET is on.
A transistor having reduced on-resistance comprising:
- a substrate of first conductivity type and having a top surface;
- spaced-apart source and drain formed in said substrate and extending to said top surface, each of second conductivity type;
- an insulating layer formed on said top surface;
- a drift region formed in said substrate between said source and said drain, being of the second conductivity type;
- a conductive gate overlying said insulating layer and a portion of said substrate between said source and said drain;
- means for impressing a voltage on said conductive gate;
- a drift electrode overlying said insulating layer and at least a portion of said drift region for selectively altering the conductivity of said drain region;
- and
- means for impressing a switchable voltage on said drift electrode, the voltage being independent of a voltage of said drain and more positive than the voltage impressed on said conductive gate when the transistor is on.
Dependencies are inferred from the claim text.