Apparatus for performing modulo arithmetic with three-port adder
AssigneeChips and Technologies, Inc.
InventorsMyron Shak, Timothy E. Decker, Jim S. Blomgren
Life of this patent
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AssigneeChips and Technologies, Inc.
InventorsMyron Shak, Timothy E. Decker, Jim S. Blomgren
Estimating the term…
A method and apparatus for emulating the intermediate 16-bit truncation of the address in the 8086 architecture using a 32-bit adder. The preferred embodiment of the invention adds the displacement, base address, and segment base values in a three-port carry save adder. The displacement value and base address are also added together in a two-port full adder. The outputs of the three-port carry save adder and two-port full adder are then compared to determine whether a carry from bit 16, if any, resulted from the addition of the displacement and base address value or the addition of the segment base value. A logic unit determines whether a carry into bit position 16 of the linear address is modified. If the carry is the result of the addition of the segment base value to the effective address, the carry is not modified. If the carry is the result of the addition of the base and displacement value, the carry is modified by forcing the bit position 16 to zero.
An apparatus for calculating a sum of a first, second and third values comprising:
An apparatus for calculating a linear address of an instruction, comprising:
A method for calculating an address from a first, second and third values comprising the steps of:
An apparatus for calculating an address from a base address, displacement and segment base values comprising:
A method for calculating an address from a first, second and third values comprising the steps of:
Dependencies are inferred from the claim text.