Integrated charge-pump phase-locked loop circuit

A method of generating an output clock signal from an input clock signal in synchronized fashion, comprising the steps of:

• comparing the phase of a feedback clock signal corresponding to said output clock signal to the input clock signal;
• generating a pump-up signal responsive to the input clock signal leading the feedback clock signal;
• generating a pump-down signal responsive to the feedback clock signal leading the input clock signal;
• generating a first rate control signal;
• generating a charging current for charging and discharging a capacitance to a voltage level responsive to said pump-up and pump-down signals, respectively, at a rate corresponding to the rate control signal;
• filtering the voltage level of said capacitance with an active filter having a slew rate dependent upon the rate control signal;
• and
• adjusting the frequency of the output clock signal corresponding to the filtered voltage level.

An integrated circuit, comprising:

• an input clock terminal;
• functional circuitry controlled by an internal clock presented at an internal clock node;
• and
• a phase-locked loop clock generator circuit for generating said internal clock at said internal clock node, comprising:
• a phase comparator, having a first input coupled to said input clock terminal for receiving an input clock signal, having a second input coupled to said internal clock node for receiving a feedback clock signal, for presenting pump-up and pump-down signals responsive to the phase difference between said input clock signal and said feedback clock signal, and for presenting a first rate control signal responsive to an occurrence of both of the pump-up and pump-down signals;
• a current source, having first and second inputs for receiving said up and down signals, respectively, and having a first control input for receiving said first rate control signal, said current source for charging a capacitance with a charging current responsive to said pump-up signal, and for discharging the capacitance with a discharging current responsive to said pump-down signal, wherein the magnitude of the charging and discharging current is controlled responsive to said first rate control signal;
• a low pass filter having an input coupled to the capacitance, and having an output stage comprising a current source controlled responsive to said first rate control signal, for presenting a frequency control signal corresponding to the voltage of the capacitance;
• and
• a voltage controlled circuit, having an input receiving said frequency control signal and having an output coupled to said internal clock node, for presenting said internal clock at a frequency corresponding to said frequency control signal.