Method of making a power VFET device using a p+ carbon doped gate layer
AssigneeTexas Instruments Incorporated
InventorsHan-Tzong Yuan, Tae S. Kim, Francis J. Morris
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Abstract
This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.
Claims14
A method of forming a vertical transistor device comprising:
- a. forming an n-type source layer;
- b. forming a p+ carbon doped gate layer over said source layer;
- c. forming a gate structure from said gate layer;
- and
- d. forming a n-type drain layer over said gate structure.
A method of forming a vertical transistor device comprising:
- a. forming an n-type source layer over a n+ substrate;
- b. forming a p+ carbon doped gate layer over said source layer;
- c. forming a gate structure from said gate layer;
- d. forming a n-type drain layer over said gate structure;
- e. forming a n+ cap layer over said drain layer;
- f. implanting a p+ dopant to contact said gate structure;
- g. forming a p-ohmic contact to said gate structure;
- h. forming an n-ohmic source contact;
- and
- i. forming an n-ohmic drain contact.
Dependencies are inferred from the claim text.