Built-in self-test (BIST) circuit

A method for testing a circuit board carrying a plurality of individual electronic circuits connected so that a first one of the circuits drives each of the others, comprising the steps of:

• (a) multiplexing input data which is normally supplied to a first electronic circuit on a circuit board, which drives each of a plurality of second electronic circuits on the board, with at least one test signal from a signature analysis register, so that during a preselected interval, the test signal is applied to the first electronic circuit which generates a response signal for propagation through to each of the second electronic circuits driven thereby, while during intervals other than the preselected interval, the input data is supplied to said first electronic circuit;
• (b) supplying the response signal from a last one of said second electronic circuits, through a delay circuit, to the signature analysis register;
• (c) delaying, at the delay, circuit an initial response signal prior to passage to the signature analysis register;
• (d) compacting, at the signature analysis register, each successive response signal with the response signals previously applied to the signature analysis register to yield a signature representative of the state of the compacted signals;
• (e) repeating the steps of (a), (b) and (d) for a prescribed number of times;
• and
• (f) comparing the signature of the compacted response signals to a signature obtained for a fault-free circuit board to detect if any faults are present.

A built-in self-test circuit for insertion within an electronic device for testing the device, comprising:

• a signature analysis register for generating test signals for input to an electronic device to cause the device to generate response signals, and for compacting such response signals to yield a signature indicative of the operation of the device;
• bypass multiplexer means coupled between the electronic device and the signature analysis register for multiplexing input data normally supplied to the electronic device with test signals from the signature analysis register, so that during preselected intervals, the test signals from the signature analysis register feed the electronic device, while during intervals other than said preselected intervals, said input data is fed to the electronic device;
• loopback multiplexing means for multiplexing the input data normally supplied to the electronic device with response signals produced by the electronic device, so that during selected intervals, the loopback multiplexing means passes the response signals, while during other than said selected intervals, the loopback multiplexing means passes the input data;
• blocking means coupled between the loopback multiplexing means and the signature analysis register for delaying transmission of an initial one of the response signals from reaching the signature analysis register for a predetermined interval;
• and
• controller means for controlling the signature analysis register, loopback multiplexing means, bypass multiplexing means, and the blocking means.