Fast programmable limit switch

A programmable controller for controlling a plurality of output states during a repetitive operation cycle comprising:

• a cycle position transducer for generating a digital position signal indicative of the position within the repetitive operation cycle;
• an offset memory connected to said cycle position transducer for storing therein a plurality of digital offset signals for each of the plurality of controlled output states, each digital offset signal indicative of an offset distance corresponding to a unique position within the repetitive operation cycle;
• a state sequencer connected to said offset memory operative to recall said digital offset signals for each of the plurality of controlled output states from said offset memory repetitively in a predetermined order;
• a digital adder connected to said cycle position transducer and said offset memory for adding said digital position signal and said recalled digital offset signal thus generating a sum position signal;
• an output state memory connected to said digital adder having a plurality of address locations, each address location storing therein an output state signal corresponding to a desired output state for a unique position within the repetitive operation cycle, said output state memory for recalling said output state signal stored in an address location indicated by said sum position signal;
• and
• an output driver connected to said output state memory and said state sequencer for producing a plurality of output states, each output state corresponding to said recalled output state signal for one of said sequence of offset values.

A programmable controller for controlling a plurality of output states during a repetitive operation cycle comprising:

• a cycle position transducer for generating a digital position signal indicative of the position within the repetitive operation cycle;
• an offset memory for storing therein separate ON and OFF digital offset signals corresponding to respective offset distances within the repetitive operation cycle for each of the plurality of controlled output states;
• a state sequencer connected to said offset memory operative to recall said ON and OFF digital offset signals for each of the plurality of controlled output states from said offset memory repetitively in a predetermined order;
• a digital adder connected to said cycle position transducer and said offset memory for adding said digital position signal and a digital offset signal recalled from said offset memory in the sequence controlled by said state sequencer thereby sequentially forming sum position signals;
• an output state memory connected to said digital adder having a plurality of address locations, each address location storing therein an output state signal corresponding to a desired output state for a unique position within the repetitive operation cycle, said output state memory for recalling said output state signal stored in an address location indicated by a sum position signal;
• a microcontroller unit connected to said offset memory and said output state memory operative to
• initialize and update said separate ON and OFF digital offset signals for each of the plurality of controlled output states stored in said offset memory,
• initialize and update said output state signals stored in said output state memory for each of said plurality of address locations;
• an output driver connected to said state sequencer and said output state memory for producing a plurality of output states, each output state corresponding to a combination of the output state signals recalled from said output state memory for respective ON and OFF offset signals for the controlled output states in the sequence determined by said state controller.