Optimized automated macro embedding for standard cell blocks
AssigneeInternational Business Machines Corporation
InventorDawn K. Dougherty
Life of this patent
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Abstract
A standard cell macro embedding method that extends the capability of conventional circuit placement routines by enabling them to automatically and optimally embed macro blocks within standard cell blocks. The macro blocks can be selected portions of the standard cell logic that are extracted and optimized for the purpose of enhancing performance, low power, density or functionality. The present invention optimally places these macros using a two pass placement process in which, first, Anchor and, second, Structure Expansion models of the macro blocks are employed to, respectively, optimally locate the macro blocks, and then, optimally place the standard cells.
Claims13
In a data processing system, a method for automatically arranging the circuits of a circuit array for placement in a semiconductor chip circuit area, the array being built up from a set of circuit elements, having an elemental logic function and a predetermined maximum spatial extent in at least one dimension, that are placed and arranged in a field corresponding to the circuit area, and for automatically embedding a predetermined circuit arrangement having a physical extent in said one dimension larger than the predetermined maximum spatial extent, comprising the steps of;
- providing a first field filler for the predetermined circuit arrangement, having a spatial extent in said one dimension no larger than the predetermined maximum spatial extent;
- placing and arranging said circuit elements and said first field filler in said field according to a predetermined algorithm;
- after arranging the circuit elements, providing at least one further field filler adjacent to said first field filler to define an aggregate field filler having an area substantially the same as the area of the predetermined circuit arrangement;
- fixing the position in the field of said aggregate field filler so that it cannot be moved in the next step;
- and then
- replacing and arranging at least some of said circuit elements in said field to account for said fixed position aggregate field filler.
In a data processing system executing a circuit placement program for a circuit array, the array being built up from a set of circuit elements having an elemental logic function and a predetermined physical size, wherein the circuit elements are placed in a semiconductor chip circuit area by a process of defining, in an area corresponding to the chip circuit area, a field of parallel limit lines having a minimal spacing therebetween determined by the tallest circuit element in the set, and placing and arranging such circuit elements along such limit lines, a method for automatically embedding a predetermined circuit arrangement having a physical height larger than the minimum spacing between the limit lines, comprising the steps of:
- defining a first field filler for the predetermined circuit arrangement, having a width substantially the same as the width of the arrangement and a height no greater than said minimum spacing between the limit lines;
- placing and arranging the circuit elements and said first field filer along said limit lines according to a predetermined algorithm;
- after performing said step of placing and arranging, providing further field fillers to said first field filler to define an aggregate field filler having an area substantially the same as the area of the predetermined circuit arrangement;
- fixing the position in the field of said aggregate field filler so that it cannot be moved in the next step;
- and
- replacing and arranging at least some of the circuit elements along said limit lines to account for said fixed position aggregate field filler.
In a data processing system, a method for automatically arranging the circuits of a circuit array for placement in a semiconductor chip circuit area, the array being built up from a set of circuit elements having an elemental logic function and a predetermined physical size, and for automatically embedding a predetermined circuit arrangement having a physical height larger than the minimum spacing between the limit lines, comprising the steps of;
- providing, in an area corresponding to the chip circuit area, a field of predefined parallel limit lines having a minimal spacing therebetween determined by the tallest circuit element in the set;
- providing a first field filler for the predetermined circuit arrangement, having a width substantially the same as the width of the arrangement and a height no greater than said minimum spacing between the limit lines;
- placing and arranging said circuit elements and said first field filler along said limit lines according to a predetermined algorithm;
- after arranging the circuit elements and said first field filler, providing further field fillers adjacent to said first field filler to define an aggregate field filler having an area substantially the same as the area of the predetermined circuit arrangement;
- fixing the position in the field of said aggregate field filler so that it cannot be moved in the next step;
- then
- placing and arranging said circuit elements along said limit lines according to said predetermined algorithm;
- substituting said predetermined circuit arrangement for said aggregate field filler;
- and
- placing wires to interconnect said cells and said predetermined circuit arrangement.
Dependencies are inferred from the claim text.