Multilayer hybrid circuit

A multilayer hybrid circuit comprising an essentially flat-shaped laminated body which includes at least one selected from a capacitor, an inductor, and a resistor, and a plurality of side terminals provided on side walls of said laminated body for external connection of said capacitor, said inductor, and said resistor,

• said capacitor including a dielectric layer and conductive layers on said dielectric layer,
• said inductor including a dielectric ferromagnetic layer and a plurality of conductive wire layers composing a coil by sandwiching said dielectric ferromagnetic layer between conductive wire layers,
• said resistor including a dielectric layer and a resistor layer deposited on said dielectric layer together with a conductive layer as a lead line,
• a coupling conductor penetrating said dielectric layers of at least one of said capacitor, said inductor, and said resistor, in perpendicular direction to the dielectric layer plane, for connecting conductive patterns on different dielectric layers,
• a plurality of said dielectric layers each having a hole to accept said coupling conductor, the positions of said holes being alternately shifted, and
• said coupling conductor comprising a plurality of elongated conductive chips in essentially S-shape through said holes in said plurality of dielectric layers, each of said conductive chips being deposited partly on an adjacent conductor chip and partly on a dielectric layer so that a succession of the conductor chips forms an elongated conductor perpendicular to the dielectric layer plane through said holes in dielectric layers.