IC testing device for permitting adjustment of timing of a test signal

An IC testing device for testing an IC under test having a plurality of IC terminals, comprising:

• a tester main body having a plurality of tester main body terminals and which derives a plurality of test signals of logical levels from a timing signal and a pattern to be applied to said IC under test, provides the test signals to said plurality of tester main body terminals corresponding to said plurality of IC terminals, compares each of a plurality of output response signals acquired from said IC terminals via said tester main body terminals with a reference voltage to determine a logic level of each output response signal, and makes a logical comparison between said logic level and an expected value pattern;
• and
• an IC connection board comprising
• a plurality of transmission lines interconnectably coupling said tester main body terminals and said IC terminals;
• and
• a nonvolatile memory for storing delay time data representative of delay times in said transmission lines of said IC connection board corresponding to said terminals of said IC under test;
• and
• wherein said tester main body is capable of adjusting timing of said test signals provided to the IC terminals and adjusting acquisition timing of said output response signals acquired from said IC terminals based on said delay time data read from said nonvolatile memory.