Timing control for precharged circuit

An analog-to-digital converter with a comparator, an auto-zero circuit, a decoder, an encoder, an output buffer in cascade, and having a precharging phase and signal transmission phase, comprising:

• a precharging section, an output section, and a transmission section connected between said precharging section and said output section,
• said precharging section comprising:
• a MOSFET driver having a precharged node connected to a precharging MOSFET load device having a gate driven from a clock pulse,
• said MOSFET load device being turned on during said precharging phase to charge said precharged node to a high logic level,
• said encoder serving as said precharging section arranged like a ROM having bit lines and word lines,
• each said bit line serving as one said precharged node,
• one of said word lines having signal "1" derived from said decoder;
• an input signal applied to the gate of said driver MOSFET for controlling said driver to be on or off during said signal transmission phase, and pulling down said precharged node if said driver is on;
• said output buffer serving as said said output section;
• a delay circuit comprising a MOSFET NAND gate having said input signal AND said precharged node voltage as inputs for controlling the timing of transmission of said transmission section until said precharged node has reached a final logical level,
• a N+1 input NAND gate having as inputs one word line signal and N bit line signals and driving two inverters serving as said delay circuit;
• said transmission section having a two input MOSFET logic gate controlled by output of two said inverters.